File:Wishbone shared bus.jpg
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Summary
Source: 'WISHBONE System-on-Chip (SoC)Interconnection Architecture for Portable IP Cores', Revision: B.3, Released: September 7, 2002, [1].
Page 3 of the spec states that: "Notice is hereby given that this document is not copyrighted, and has been placed into the public domain. It may be freely copied and distributed by any means."
Licensing
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This work has been released into the public domain by its author, opencores.org. This applies worldwide. In some countries this may not be legally possible; if so: opencores.org grants anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law.
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 16:40, 18 November 2007 | | 598 × 151 (14 KB) | wikimediacommons>Eeinfo2008 | Source: 'WISHBONE System-on-Chip (SoC)Interconnection Architecture for Portable IP Cores', Revision: B.3, Released: September 7, 2002, [http://www.opencores.org/projects.cgi/web/wishbone/wbspec_b3.pdf wbspec_b3.pdf]. Page 3 of the spec states that: "Noti |
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