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{{Short description|Amiga 3000 expansion bus}}
{{Primary sources|date=January 2019}}
The '''Zorro III''' is a [[computer bus]] specification, introduced in 1990 with the [[Amiga 3000]]. As an [[expansion bus]], it is used to attach [[computer peripheral|peripheral]] devices to an Amiga [[motherboard]]. Designed by [[Commodore International]] lead engineer [[Dave Haynie]], the [[32-bit]] Zorro III replaced the [[16-bit]] [[Zorro II]] bus used in the [[Amiga 2000]]. As with the Zorro II bus, Zorro III allows for true Plug and Play autodetection (similar to, and prior to, the PC's [[Peripheral Component Interconnect|PCI]] bus) wherein devices are dynamically allocated the resources they need on boot.

== Details ==
Zorro III continued Zorro II's direct memory-mapped address design (unlike [[x86|80x86]] processors, the [[Motorola 68000|MC68K]] family used in the Amiga does not have a separate I/O address mechanism). Just as with Zorro II on 24-bit systems, Zorro III reserves a large chunk of 32-bit real memory [[address space]] for large memory mapped cards, a smaller chunk with smaller allocation granularity for "I/O" type board. Zorro III was never supported on 24-bit address or 16-bit data devices—it requires a full 32-bit CPU. The CPU can directly address any Zorro III device as memory, so Zorro memory expansions could be made (and were made) as well as it being possible to use video memory on a video card to be as system [[Random access memory|RAM]].

As an asynchronous bus, Zorro III specifies bus cycles of set lengths during which a transaction conforming to the specifications of the bus can be carried out. The initial implementation of Zorro III was in Commodore's "Fat" [[Amiga_custom_chips#Buster|Buster]] (BUS conTrollER) gate array, assisted by a very high speed [[Programmable Array Logic|PAL]] and numerous [[Transistor–transistor logic|TTL]] buffer chips for bus buffering, isolation, and multiplexing. The [[Amiga 4000]] implementation is fundamentally the same, but integrates a second [[gate array|gate-array]] to replace the TTL buffers. The Buster chip provides bus arbitration, translation between the [[MC68030]] bus protocols and either Zorro II or Zorro III bus cycles (geographically mapped based on the Zorro bus address), and a vectored [[interrupt]] mechanism, generally not used. Zorro II bus masters are legal bus hogs, but Zorro III devices are fairly arbitrated and have controller-limited bus tenure.

Despite being a 32-bit bus, Zorro III uses the same 100 way slot and [[edge connector]] as Zorro II. The extra address and data lines are provided by multiplexing some of the existing connections with the nature of the lines changing at different stages of the bus access cycle (e.g. address becoming data). However, the bus is not fully multiplexed; the lower 8-bits of address are available during data cycles, which allows Zorro III to support a fast burst cycle in page-mode. Properly designed Zorro II expansion cards can coexist with Zorro III cards; it is not a requirement of a Zorro III bus master to support [[Direct memory access|DMA]] access to Zorro II bus targets. Cards can detect a Zorro III vs. Zorro II backplane, allowing certain Zorro III cards to function when connected to the older Zorro II bus, though at Zorro II's reduced data rates.

The Zorro III bus has a theoretical bandwidth of 150 [[Data-rate_units#Megabyte_per_second|MByte/s]], based on an ideal Zorro III [[Master–slave (technology)|master and slave]] device running with minimum setup and hold times.<ref>[[Dave Haynie]], designer of the Zorro III bus, claims in [https://groups.google.com/group/comp.sys.amiga/msg/c532a74c1fa3f992?dmode=source this] posting that the theoretical max of the Zorro III bus can be derived by the timing information given in ''chapter 5'' of the [http://www.thule.no/haynie/zorroiii/docs/zorro3.pdf Zorro III technical specification] {{Webarchive|url=https://web.archive.org/web/20120716212151/http://www.thule.no/haynie/zorroiii/docs/zorro3.pdf |date=2012-07-16 }}.</ref><ref>Dave Haynie, designer of the Zorro III bus, claims in [https://groups.google.com/group/comp.sys.amiga.advocacy/msg/42ecbcbae063cfe1?dmode=source this] posting that Zorro III is an [[Asynchronous communication|asynchronous]] bus and with that does not have a classical MHz rating. A maximum theoretical MHz value may be derived by examining timing constraints detailed in the [http://www.thule.no/haynie/zorroiii/docs/zorro3.pdf Zorro III technical specification] {{Webarchive|url=https://web.archive.org/web/20120716212151/http://www.thule.no/haynie/zorroiii/docs/zorro3.pdf |date=2012-07-16 }}, which should yield about 37.5 MHz. No existing implementation performs to this level.</ref><ref>Dave Haynie, designer of the Zorro III bus, claims in [https://groups.google.com/group/comp.sys.amiga.hardware/msg/03b8cec336310e4a?dmode=source this] posting that Zorro III has a max burst rate of 150 MB/s.</ref> The real transfer speed between the Amiga 3000/4000 implementation of Zorro III and a Zorro III card is somewhere around 13.5 MByte/s due to the limitations of the Buster chip.<ref>{{Cite web |url=http://www.amiga.org/forums/showthread.php?p=563681#post563681 |title=amiga.org post by Michael Boehmer on real-life Zorro III speed |access-date=2013-03-19 |archive-url=https://web.archive.org/web/20120229182347/http://www.amiga.org/forums/showthread.php?p=563681#post563681 |archive-date=2012-02-29 |url-status=dead }}</ref> This was comparable to [[Intel]]'s first PCI implementation, which peaked at 25 MByte/s. Zorro III was optimized for future single-chip implementations of the protocol, but the resources available at Commodore in 1990 limited the initial implementation.

This is also the limiting factor with third-party Amiga [[Conventional PCI|PCI]] expansion boards like e.g. Elbox Mediator PCI or the Matay Prometheus PCI (about 12 MByte/s PCI to 68k-system). DMA transfers between two Zorro III cards (or PCI cards on an PCI expansion board) can be much faster.<ref>[http://amiga.czex.com/local2001-2002/2_4prometheus.html czex.com - Prometheus FAQ]</ref>

== Memory map ==
{| class="wikitable"
|-
! Address || Size [MByte] || Description
|-
|-
|align="right"| 0x0000 0000
|align="right"| 2.0 || [[Amiga Chip RAM|Chip memory]]
|-
|align="right"| 0x0020 0000
|align="right"| 8.0 || Zorro II memory expansion space
|-
|align="right"| 0x00A0 0000
|align="right"| 1.5 || Zorro II I/O expansion space
|-
|align="right"| 0x00B8 0000
|align="right"| 3.0 || [[Amiga 2000|A2000]] motherboard register space
|-
|align="right"| 0x00E8 0000
|align="right"| 0.5 || [[Amiga Zorro II|Zorro II]] I/O
|-
|align="right"| 0x00F0 0000
|align="right"| 1.0 || Motherboard [[read-only memory|ROM]]
|-
|align="right"| 0x0100 0000
|align="right"| 112.0 || [[Amiga 3000|A3000]] motherboard space
|-
|align="right"| 0x0800 0000
|align="right"| 128.0 || 32-Bit memory expansion space
|-
|align="right"| 0x1000 0000
|align="right"| 1792.0 || Zorro III expansion space <ref name="thule_no_zorro3">{{cite web | title=The Zorro III Bus Specification | url=http://www.thule.no/haynie/zorroiii/docs/zorro3.pdf | first=Dave | last=Haynie | date=20 March 1991 | publisher=Commodore-Amiga, Inc. | access-date=4 January 2008 | archive-url=https://web.archive.org/web/20120716212151/http://www.thule.no/haynie/zorroiii/docs/zorro3.pdf | archive-date=16 July 2012 | url-status=dead }} 090430 thule.no p16 fig1-1</ref>
|-
|align="right"| 0x8000 0000
|align="right"| 2032.0 || Reserved
|-
|align="right"| 0xFF00 0000
|align="right"| 64 KB || Zorro III Configuration unit
|-
|align="right"| 0xFF01 0000
|align="right" rowspan="2"| 16.0
|rowspan="2"| Reserved <ref name="thule_no-a3000p">{{cite web|title=The Amiga 3000+ System Specification An enhanced Amiga 3000 family computer Document Revision 0.6 1991 DevCon Release by Dave Haynie July 17, 1991 Copyright 1991 Commodore-Amiga, Inc.|url=http://www.thule.no/haynie/research/a3000p/docs/a3000p.pdf|access-date=May 1, 2009|archive-url=https://web.archive.org/web/20120716212022/http://www.thule.no/haynie/research/a3000p/docs/a3000p.pdf|archive-date=July 16, 2012|url-status=dead}} 090501 thule.no p14</ref>
|-
|align="right"| 0xFFFF FFFF
|}

== Physical ==
The physical connector is a standard {{convert|0.1|in|mm|abbr=on|order=flip}} spaced card edge connector with 2 × 50 rows of pins.<ref name="eab_abime_net-showthread_php_p_411339">{{cite web|title=Replacement zorro slots? - English Amiga Board|url=http://eab.abime.net/showthread.php?p=411339}} 090501 eab.abime.net</ref>

Power:
{| class="wikitable" style="text-align:center"
|-
! [Volt] || [Ampere]
|-
| {{0}}+5 || {{0|< }}2.0
|-
| {{0}}−5 || < 0.3
|-
| +12 || < 8.0
|-
| −12 || < 0.3
|}<ref name="thule_no_zorro3" />

==See also==
{{Portal|Amiga}}
*[[List of interface bit rates#Computer buses]]

==References==
{{Reflist}}

== External links ==
* [https://web.archive.org/web/20120716212151/http://www.thule.no/haynie/zorroiii/docs/zorro3.pdf The Zorro III Bus Specification (PDF), thule.no]
* [http://amiga.resource.cx/exp/search.pl?intf=z3 Amiga Hardware Database Descriptions and photos of Zorro III cards, amiga.resource.cx]
* [http://amigahardware.mariomisic.de/index_e.html The Big Book of Amiga Hardware, amigahardware.mariomisic.de]

{{Amiga hardware}}
{{Computer-bus}}

[[Category:Amiga|Zorro III]]
[[Category:Computer buses]]
[[Category:Motherboard expansion slot]]

Zorro III - Revision history

RS-485: Imported from Wikipedia (overwrite)