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{{Short description|Open source circuitry hardware}}
{{Infobox Computer Hardware Bus
| name = Wishbone
| fullname =
| image =
| caption =
| invent-date =
| invent-name = Silicore Corporation
| super-name =
| super-date =
| width = 8, 16, 32, 64
| numdev =
| speed =
| style = p
| hotplug = No (On chip bus)
| external = No
}}
[[File:Wishbone Interface.svg|thumb|343px|right|Master and Slave Wishbone's interfaces.]]
The '''Wishbone Bus''' is an [[open source hardware]] [[computer bus]] intended to let the parts of an [[integrated circuit]] communicate with each other. The aim is to allow the connection of differing [[Semiconductor intellectual property core|cores]] to each other inside of a chip. The '''Wishbone Bus''' is used by many designs in the [[OpenCores]] project.

Wishbone is intended as a "logic bus". It does not specify electrical information or the bus topology. Instead, the specification is written in terms of "signals", clock cycles, and high and low levels.

This ambiguity is intentional. Wishbone is made to let designers combine several designs written in [[Verilog]], [[VHDL]] or some other logic-description language for [[electronic design automation]] (EDA). Wishbone provides a standard way for designers to combine these [[hardware logic]] designs (called "cores").
Wishbone is defined to have 8, 16, 32, and 64-bit buses. All signals are synchronous to a single clock but some slave responses must be generated [[Combinational logic|combinatorially]] for maximum performance. Wishbone permits addition of a "tag bus" to describe the data. But reset, simple addressed reads and writes, movement of blocks of data, and indivisible bus cycles all work without tags.

Wishbone is [[Open-source software|open source]]. To prevent preemption of its technologies by aggressive patenting, the Wishbone specification includes examples of [[prior art]], to prove its concepts are in the public domain.

A device does not ''conform'' to the Wishbone specification unless it includes a ''data sheet'' that describes what it does, bus width, utilization, etc. Promoting reuse of a design requires the data sheet. Making a design reusable in turn makes it easier to share with others.

The [[Simple Bus Architecture]] is a simplified version of the Wishbone specification.<ref>
Simple Bus Architecture, 2015</ref>

==Wishbone topologies==
Wishbone adapts well to common topologies such as point-to-point, many-to-many (i.e. the classic bus system), hierarchical, or even switched fabrics such as [[crossbar switch]]es. In the more exotic topologies, Wishbone requires a bus controller or arbiter, but devices still maintain the same interface.<ref>Miti & Stojcev, 2006</ref><ref>Wishbone B4, 2010, pp. 17, 21</ref>

===Shared bus===
[[image:wishbone_shared_bus.jpg]]

===Data flow===
[[image:wishbone_pipeline.jpg]]

===Crossbar switch===
[[image:wishbone_cross_bar.jpg]]

==Comparisons==
{{More citations needed section|date=June 2025|talk=impossibility of this mapping between Wishbone and Avalon}}
Wishbone control signals are compared to other system on a chip (SoC) bus standards in the below table:<ref>Wishbone B4, 2010, pp. 28-30</ref>

{|class="wikitable"
|+Wishbone → Avalon
! Wishbone
! Avalon Bus
! Description
|-
| '''cyc'''
| <nowiki>= !write_n or !read_n</nowiki>
| indicates that a valid bus cycle is in progress
|-
| '''stb'''
| = chipselect
| indicates a valid data transfer cycle
|-
| '''we'''
| = !write_n and read_n
| indicates whether the current local bus cycle is a READ or WRITE cycle. The signal is negated during READ cycles, and is asserted during WRITE cycles.
|-
| '''ack'''
| = !waitrequest
| indicates the termination of a normal bus cycle by slave device.
|}

{|class="wikitable"
|+ Avalon → Wishbone
! Avalon Bus
! Wishbone
! Description
|-
| '''chipselect'''
| = stb
| indicates that slave device is selected.
|-
| '''write_n'''
| = !(cyc and we)
| indicated that master requests to write to slave device.
|-
| '''read_n'''
| = !(cyc and !we)
| indicated that master requests to read from slave device.
|-
| '''waitrequest'''
| = !ack
| indicates that slave requests that master wait.
|}

==See also==
* [[Master/slave (technology)]]
* [[Advanced eXtensible Interface]]

==Notes==
{{reflist}}

==References==
*{{Cite web |year=2015 |title=SBA - Simple Bus Architecture |url=https://sba.accesus.com/ |website=sba.accesus.com |language=en-US}}
*{{Cite journal |last1=Miti |first1=Milica |last2=Stojcev |first2=Mile |date=2006 |title=An Overview of On-Chip Buses |url=https://www.researchgate.net/publication/237587431 |journal= Facta Universitatis - Series: Electronics and Energetics|volume=19 |issue=3 |pages=405–428 |doi=10.2298/FUEE0603405M |via=ResearchGate|doi-access=free }}
*{{Citation |title=Wishbone B4: WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores |year=2010 |url=https://cdn.opencores.org/downloads/wbspec_b4.pdf |archive-url=https://web.archive.org/web/20250518085442/https://cdn.opencores.org/downloads/wbspec_b4.pdf |archive-date=May 18, 2025 |url-status=live |publisher=OpenCores}}

==External links==
* [https://cdn.opencores.org/downloads/wbspec_b3.pdf Wishbone Version B3]- An older revision of the specification
* [https://cdn.opencores.org/downloads/appnote_01.pdf appnote_01]- Combining WISHBONE interface signals application note
* [https://cdn.opencores.org/downloads/soc_bus_comparison.pdf Comparison to other SoC buses]
* [https://opencores.org/howto/wishbone Wishbone@OpenCores]
* [https://www.fpga-cores.com/wishbone/ Wishbone@FPGA-Cores.com]

{{Computer-bus}}

[[Category:Computer buses]]
[[Category:Open hardware electronic devices]]

Wishbone (computer bus) - Revision history

RS-485: Imported from Wikipedia (overwrite)