RS-485: Imported from Wikipedia (overwrite)

2026-05-03T07:32:23Z

Imported from Wikipedia (overwrite)

New page

{{short description|Single computer bus that connects the major components of a computer system}}
[[Image:Computer system bus.svg |thumb|right|upright=1.6 |Example of a single system [[Bus (computing)|computer bus]] ]]{{More citations needed|date=August 2025}}
A '''system bus''' is a single [[Bus (computing)|computer bus]] that connects the major components of a computer system,
combining the functions of a [[Memory bus|data bus]] to carry information, an [[address bus]] to determine where it should be sent or read from, and a [[control bus]] to determine its operation. The technique was developed to reduce costs and improve modularity, and although popular in the 1970s and 1980s, more modern computers use a variety of separate buses adapted to more specific needs.<ref>{{Cite web |title=Buses - Computer structure - Higher Computing Science Revision |url=https://www.bbc.co.uk/bitesize/guides/zr8kt39/revision/3 |access-date=2025-08-10 |website=BBC Bitesize |language=en-GB}}</ref>

The '''system level bus''' (as distinct from a CPU's internal [[datapath]] busses) connects the CPU to memory and I/O devices.<ref>
Edward Bosworth.
[http://www.edwardbosworth.com/My5155Text_V07_HTM/MyText5155_Ch10_V07.htm "Chapter 10 – Overview of Busses"].
</ref>
Typically a system level bus is designed for use as a [[backplane]].<ref>
Hui Wu.
[http://www.cse.unsw.edu.au/~cs2121/LectureNotes/Lect20.pdf "Computer Buses and Parallel Input/Output"].
2006.
</ref>

==Background scenario==
Many of the computers were based on the ''[[First Draft of a Report on the EDVAC]]'' report published in 1945. In what became known as the [[Von Neumann architecture]], a central control unit and [[arithmetic logic unit]] (ALU, which he called the central arithmetic part) were combined with [[computer memory]] and [[input/output|input and output]] functions to form a [[stored program computer]].<ref>{{cite web |title= First Draft of a Report on the EDVAC |author= John von Neumann |date= June 30, 1945 |url= http://qss.stanford.edu/~godfrey/vonNeumann/vnedvac.pdf |access-date= May 27, 2011 |url-status= dead |archive-url= https://web.archive.org/web/20130314123032/http://qss.stanford.edu/~godfrey/vonNeumann/vnedvac.pdf |archive-date= March 14, 2013 |author-link= John von Neumann }} Introduction and editing by Michael D. Godfrey, Stanford University, November 1992.</ref> The ''Report'' presented a general organization and theoretical model of the computer, however, not the implementation of that model.<ref>{{cite journal |title= The Computer as von Neumann Planned It |author1= Michael D. Godfrey |author2= D. F. Hendry |year= 1993 |journal= IEEE Annals of the History of Computing |volume= 15 |number= 1 |pages= 11–21 |url= http://qss.stanford.edu/~godfrey/vonNeumann/edv-an.pdf |doi= 10.1109/85.194088 |s2cid= 569933 |url-status= dead |archive-url= https://web.archive.org/web/20110825104605/http://qss.stanford.edu/~godfrey/vonNeumann/edv-an.pdf |archive-date= 2011-08-25 }}</ref>
Soon designs integrated the control unit and ALU into what became known as the [[central processing unit]] (CPU).

Computers in the 1950s and 1960s were generally constructed in an ad-hoc fashion.
For example, the CPU, memory, and input/output units were each one or more cabinets connected by cables. Engineers used the common techniques of standardized bundles of wires and extended the concept as [[backplane]]s were used to hold [[printed circuit board]]s in these early machines.
The name "bus" was already used for "[[busbar|bus bars]]" that carried electrical power to the various parts of electric machines, including early mechanical calculators.<ref>{{US Patent |3470421}} "Continuous Bus Bar for Connector Plate Back Panel Machine Wiring" Donald L. Shore et al., Filed August 30, 1967, issued September 30, 1969.</ref>
The advent of [[integrated circuit]]s vastly reduced the size of each computer unit, and buses became more standardized.<ref>{{US Patent |3462742}} "Computer System Adapted to be Constructed of Large Integrated Circuit Arrays" Henry S. Miller et al., Filed December 21, 1966, issued August 19, 1969.</ref>
Standard modules could be interconnected in more uniform ways and were easier to develop and maintain.

==Description==
To provide even more modularity with reduced cost, [[memory bus|memory]] and [[I/O bus]]es (and the required [[control bus|control]] and [[power bus]]es) were sometimes combined into a single unified system bus.<ref>{{cite book |title=The essentials of computer organization and architecture |author1=Linda Null |author2=Julia Lobur |publisher=Jones & Bartlett Learning |year=2010 |isbn= 978-1-4496-0006-8 |edition= 3rd |pages= 36,199–203 |url= https://books.google.com/books?id=f83XxoBC_8MC&pg=PA36 }}</ref>
Modularity and cost became important as computers became small enough to fit in a single cabinet (and customers expected similar price reductions).
[[Digital Equipment Corporation]] (DEC) further reduced cost for mass-produced [[minicomputer]]s, and [[memory-mapped I/O]] into the memory bus, so that the devices appeared to be memory locations. This was implemented in the [[Unibus]] of the [[PDP-11]] around 1969, eliminating the need for a separate I/O bus.<ref>{{cite journal |title= A New Architecture for Mini-Computers—The DEC PDP-11 |author1= C. Gordon Bell |author2= R. Cady |author3= H. McFarland |author4= B. Delagi |author5= J. O'Laughlin |author6= R. Noonan |author7= W. Wulf |journal= Spring Joint Computer Conference |pages= 657–675 |year= 1970 |url= http://research.microsoft.com/en-us/um/people/gbell/CGB%20Files/New%20Architecture%20PDP11%20SJCC%201970%20c.pdf }}</ref>
Even computers such as the [[PDP-8]] without memory-mapped I/O were soon implemented with a system bus, which allowed modules to be plugged into any slot.<ref>{{cite book |title= Small Computer Handbook |publisher= Digital Equipment Corporation |year= 1973 |pages= 2–9 |url= http://www.bitsavers.org/pdf/dec/pdp8/handbooks/Small_Computer_Handbook_1973.pdf }}</ref>
Some authors called this a new streamlined "model" of computer architecture.<ref>{{cite book |title= Computer architecture and organization: an integrated approach |author1= Miles J. Murdocca |author2= Vincent P. Heuring |page= 11 |publisher= John Wiley & Sons |year= 2007 |isbn= 978-0-471-73388-1 }}</ref>

Many early microcomputers (with a CPU generally on a single [[integrated circuit]]) were built with a single system bus, starting with the [[S-100 bus]] in the [[Altair 8800]] computer system in about 1975.<ref>{{cite web |title= Origins of S-100 computers |author= Herbert R. Johnson |url= http://retrotechnology.com/herbs_stuff/s_origins.html }}</ref>
The [[IBM PC]] used the [[Industry Standard Architecture]] (ISA) bus as its system bus in 1981. The passive backplanes of early models were replaced with the standard of putting the CPU and RAM on a [[motherboard]], with only optional [[daughterboard]]s or [[expansion card]]s in system bus slots.

[[Image:Shared memory.svg |thumb |upright=1.6 | Simple [[symmetric multiprocessing]] using a system bus ]]
The [[Multibus]] became a standard of the [[Institute of Electrical and Electronics Engineers]] as IEEE standard 796 in 1983.<ref>{{cite web |title= 796-1983 — IEEE Standard Microcomputer System Bus |publisher= [[Institute of Electrical and Electronics Engineers]] |year= 1983 |url= https://standards.ieee.org/ieee/796/1021/ |access-date= May 25, 2011 }}</ref>
[[Sun Microsystems]] developed the [[SBus]] in 1989 to support smaller expansion cards.<ref>{{cite book |doi= 10.1109/CMPCON.1990.63672 |chapter= The SBus: Sun's high performance system bus for RISC workstations |title= Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage |pages= 189–194 |year= 1990 |last1= Frank |first1= E.H. |isbn= 0-8186-2028-5 |s2cid= 25815415 }}</ref>
The easiest way to implement [[symmetric multiprocessing]] was to plug in more than one CPU into the shared system bus, which was used through the 1980s.
However, the shared bus quickly became the bottleneck and more sophisticated connection techniques were explored.<ref>{{cite book |title= Bus and Cache Memory Organization for Multiprocessors |author= Donald Charles Winsor |year= 1989 |publisher= University of Michigan Electrical Engineering department |url= http://www.eecs.umich.edu/~tnm/trev_test/dissertationsPDF/donw.pdf |access-date= 2011-05-29 |archive-date= 2012-01-28 |archive-url= https://web.archive.org/web/20120128235658/http://www.eecs.umich.edu/~tnm/trev_test/dissertationsPDF/donw.pdf |url-status= dead }} Ph.D. dissertation.</ref>

Even in very simple systems, at various times the data bus is driven by the program memory, by RAM, and by I/O devices.
To prevent [[bus contention]] on the data bus, at any one instant only one device drives the data bus.
In very simple systems, only the data bus is required to be a bidirectional bus.
In very simple systems, the [[memory address register]] always drives the address bus, the [[control unit]] always drives the control bus,
and an [[address decoder]] selects which particular device is allowed to drive the data bus during this bus cycle.
In very simple systems, every [[instruction cycle]] starts with a READ memory cycle where program memory drives the instruction onto the data bus while the [[instruction register]] latches that instruction from the data bus.
Some instructions continue with a WRITE memory cycle where the [[memory data register]] drives data onto the data bus into the chosen RAM or I/O device.
Other instructions continue with another READ memory cycle where the chosen RAM, program memory, or I/O device drives data onto the data bus while the memory data register latches that data from the data bus.

More complex systems have a [[multi-master bus]]—not only do they have many devices that each drive the data bus, but also have many [[bus master]]s that each drive the address bus.
The address bus as well as the data bus in [[bus snooping]] systems is required to be a bidirectional bus, often implemented as a [[three-state bus]].
To prevent bus contention on the address bus, a [[bus arbiter]] selects which particular bus master is allowed to drive the address bus during this bus cycle.

==Dual Independent Bus==
[[Intel]] has used the term ''Dual Independent Bus'' (DIB) for two different purposes. The first one came when Intel changed from a single [[local bus]] to the DIB, using the external [[front-side bus]] to the main system [[Computer data storage|memory]] and I/O devices, and the internal [[back-side bus]] to the L2 [[CPU cache]]. This was introduced in the [[Pentium Pro]] in 1995.<ref>[https://www.intel.com/pressroom/archive/releases/1997/CN040997.HTM Intel's CEO Reveals New Bus Architecture To Be Implemented In Upcoming Pentium® II Microprocessor]</ref><ref>{{cite web |title= Introduction to Intel Architecture: The Basics |author= Todd Langley and Rob Kowalczyk |date= January 2009 |url= ftp://download.intel.com/design/intarch/PAPERS/321087.pdf |publisher= Intel Corporation |work= White paper |archive-url= https://web.archive.org/web/20090712091351/http://download.intel.com:80/design/intarch/papers/321087.pdf |archive-date= 2009-07-12 |url-status= dead |access-date= May 25, 2011 }}</ref><ref>{{cite magazine |title=Accelerated Graphics Port |magazine=[[Next Generation (magazine)|Next Generation]]|issue=37|publisher=[[Imagine Media]] |date=January 1998 |pages=94–96}}</ref>

In 2005 and 2006 Intel introduced the 8500 and 5000 chipsets, where DIB referred to the two [[front-side bus]]es on a chipset, which doubles the system bandwidth compared to having just one FSB shared by all the CPUs. However, the information needed to guarantee the [[cache coherence]] of shared data located in different caches have to be sent in broadcast (snooped) to check the other FSB's CPUs' cache state, reducing the available bandwidth. To reduce the coherency traffic, a [[snoop filter]] was included in the higher-end chipsets, in order to have cache state information available on-chipset. In 2007 Intel extended the idea of multiple buses in the 7300 chipset with four independent FSBs, calling it ''dedicated high-speed interconnects'' (DHSI).<ref>[https://www.intel.com/content/www/us/en/io/quickpath-technology/quick-path-interconnect-introduction-paper.html An Introduction to the Intel® QuickPath Interconnect], Figures 4 and 5.</ref>

The system bus approach is obsolete in the modern personal and server computers, which instead use higher-performance interconnection technologies such as [[HyperTransport]] and [[Intel QuickPath Interconnect]], while the system bus architecture continued to be used on simpler embedded microprocessors.
The systems bus can even be internal to a single integrated circuit, producing a [[system-on-a-chip]]. Examples of on-chip bus include [[Advanced Microcontroller Bus Architecture|AMBA]], [[CoreConnect]], [[Wishbone (computer bus)|Wishbone]], and modified versions of [[PCI bus|PCI]] or [[PCIe]].<ref>{{cite web |title= OpenCores SoC Bus Review |author= Rudolf Usselmann |date= January 9, 2001 |url= http://opencores.org/cdn/downloads/soc_bus_comparison.pdf |access-date= May 30, 2011 }}</ref>

== Examples ==

=== Intel Direct Media Interface ===
{{Unreferenced section|date=June 2023}}
[[Direct Media Interface]] is an example of a system bus (besides directly accessed [[PCI Express|PCIE]] lanes) implemented by Intel and known since at least 2004. It's primarily used to access [[Memory-mapped I/O and port-mapped I/O|memory-mapped I/O]] devices and communicate CPU to the [[chipset]].

== See also ==
* [[Bus (computing)]]
* [[External Bus Interface]]
* [[Expansion bus]]

==References==
{{Reflist}}

{{Computer-bus}}

[[Category:Computer buses]]

System bus - Revision history

RS-485: Imported from Wikipedia (overwrite)