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Imported from Wikipedia (overwrite)

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{{short description|8-bit microprocessor}}
{{Infobox CPU
|name = Signetics 2650
|image = KL Signetics 2650AN.jpg
|caption = Signetics 2650AN
|produced-start = {{Start date and age|1975}}
|produced-end =
|slowest = 1.2 | slow-unit = MHz
|fastest =
|manuf1 = [[Signetics]], [[Philips]]
|arch =
|transistors =
|instructions =
|data-width = 8
|address-width = 15
|pack1 = 40-pin [[Dual in-line package|DIP]]
}}

The '''Signetics 2650''' was an [[8-bit]] [[microprocessor]] introduced in July 1975.<ref>{{Cite web |url=http://bitsavers.trailing-edge.com/pdf/microcomputerAssociates/Microcomputer_Digest_v02n01_Jul75.pdf |title=Microcomputer Digest Vol. 2 No. 1 July 1975 |access-date=1 February 2014 |archive-url=https://web.archive.org/web/20140201234414/http://bitsavers.trailing-edge.com/pdf/microcomputerAssociates/Microcomputer_Digest_v02n01_Jul75.pdf |archive-date=1 February 2014 |url-status=live }}</ref> According to [[Adam Osborne]]'s book ''An Introduction to Microprocessors Vol 2: Some Real Products'', it was "the most [[minicomputer]]-like" of the microprocessors available at the time. A combination of missing features and odd memory access limited its appeal, and the system saw little use in the market.

==Development==
[[File:Locale_RS6_Signetics 2650 microprocessor October 1975.jpg|thumb|300px|right|Signetics 2650 introductory ad, October 30, 1975]]

In 1972, Signetics' Jack Curtis{{efn|Best known for his joke article on [[Write-only_memory_(joke)|write-only memory]].}} hired John Kessler of [[IBM]] to lead the design of a new single-chip CPU intended to compete with [[minicomputer]] systems. Kessler selected the [[IBM 1130]] as the model for the new design. The 1130, released in 1965, was a [[16-bit]] [[minicomputer]] that shared many design features with other minis of the era.<ref name=shack/>

While Kessler designed the architecture, Kent Andreas laid out the CPU using a recently developed [[ion implantation]] [[NMOS logic|NMOS]] process. In contrast to the far more common [[PMOS logic|PMOS]] process of the era, NMOS used less power and dissipated less heat. This allowed the chip to be run at higher speeds than PMOS CPU designs, and the first 2650's ran at the same 1.25 MHz speed as the contemporary models of the 1130.<ref name=shack/>

When it was designed in 1972, the 2650 was among the most advanced designs on the market, easily outperforming and out-featuring the [[Intel 4004]] and [[Intel 8008|8008]] of the same era. Despite this, the design was not released to production. At the time, Signetics was heavily involved with [[Dolby Laboratories]], developing [[integrated circuit]]s that implemented Dolby's suite of [[Dolby noise-reduction system|noise-reduction system]]s. Production of the 2650 was pushed back, and the CPU was not formally introduced until July 1975. By 1975, several new CPUs had been introduced, designed from the start to be 8-bit machines rather than mimicking an older design, and the 2650's advantages were no longer as compelling.<ref name=shack/>

In 1975, [[Philips]] purchased Signetics, and from that point versions of the 2650 can be found with both Signetics or Philips branding.<ref name=shack/>

In March 1976, Signetics reached a second-source agreement with [[Advanced Memory Systems]] (AMS). At that time, most CPU firms were very small and no one would buy a design from a company that might go bankrupt. Second-sourcing was an important guarantee that the design would remain available in this eventuality. AMS was already acting as a second-source for the [[RCA 1802]], an advanced [[CMOS]] design. The NMOS 2650 was seen as a useful adjunct that would not directly compete with the 1802. Unfortunately, in November AMS was purchased by [[Intersil]], who had their own [[Intersil 6100]], a single-chip version of the [[PDP-8]] mini. Intersil dropped production of the 2650.<ref name=shack/>

Signetics tried again with [[National Semiconductor]] in 1977, who planned to introduce versions in the last quarter of the year. For unknown reasons, this appears to have never happened, and only a single example of an NS version, from France, has ever been found.<ref name=shack/>

Signetics continued the development of the 2650, introducing two new models in 1977. The 2650A was a reworked version of the original layout intended to improve yield, and thus reduce cost. Speed remained unchanged at 1.25 MHz for the base model and 2 MHz for the -1 versions. The 2650B was based on the A, added two new instructions, and improved the performance of a number of existing instructions.<ref name=shack/>

==Description==
[[File:Locale_RS6_Signetics 2650A die.JPG|thumb|right|Signetics 2650A chip magnified.]]

{| class="infobox" style="font-size:88%;width:31em;"
|+ Signetics 2650 registers
|-
| style="text-align:center;"| 14
| style="text-align:center;"| 13
| style="text-align:center;"| 12
| style="text-align:center;"| 11
| style="text-align:center;"| 10
| style="text-align:center;"| 09
| style="text-align:center;"| 08
| style="text-align:center;"| 07
| style="text-align:center;"| 06
| style="text-align:center;"| 05
| style="text-align:center;"| 04
| style="text-align:center;"| 03
| style="text-align:center;"| 02
| style="text-align:center;"| 01
| style="text-align:center;"| 00
| ''(bit position)''
|-
|colspan="16" | '''Main general purpose registers''' 
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="7" |  
| style="text-align:center;" colspan="8"| REG0
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="7" |  
| style="text-align:center;" colspan="8"| REG1
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="7" |  
| style="text-align:center;" colspan="8"| REG2
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="7" |  
| style="text-align:center;" colspan="8"| REG3
|-
|colspan="16" | '''Alternate general purpose registers''' 
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="7" |  
| style="text-align:center;" colspan="8"| REG1'
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="7" |  
| style="text-align:center;" colspan="8"| REG2'
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="7" |  
| style="text-align:center;" colspan="8"| REG3'
|-
|colspan="16" | '''Instruction Address register''' 
|- style="background:silver;color:black"
| style="text-align:center;" colspan="2"| Page
| style="text-align:center;" colspan="13"|
|-
|colspan="16" | '''Subroutine return address stack''' 
|- style="background:silver;color:black"
| style="text-align:center;" colspan="15"| S0
|-
|- style="background:silver;color:black"
| style="text-align:center;" colspan="15"| S1
|-
|- style="background:silver;color:black"
| style="text-align:center;" colspan="15"| S2
|-
|- style="background:silver;color:black"
| style="text-align:center;" colspan="15"| S2
|-
|- style="background:silver;color:black"
| style="text-align:center;" colspan="15"| S4
|-
|- style="background:silver;color:black"
| style="text-align:center;" colspan="15"| S5
|-
|- style="background:silver;color:black"
| style="text-align:center;" colspan="15"| S6
|-
|- style="background:silver;color:black"
| style="text-align:center;" colspan="15"| S7
|-
|colspan="16" | '''Program Status Words'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="7" |  
| style="text-align:center;"| S
| style="text-align:center;"| F
| style="text-align:center;"| II
| style="text-align:center;" colspan="2"|
| style="text-align:center;" colspan="3"| Stack Ptr
| style="background:white; color:black" | PSU

|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="7" |  
| style="text-align:center;" colspan="2"| CC
| style="text-align:center;"| ID
| style="text-align:center;"| RS
| style="text-align:center;"| WC
| style="text-align:center;"| OV
| style="text-align:center;"| CM
| style="text-align:center;"| C
| style="background:white; color:black" | PSL
|}

The overall design of the 2650 was based on the [[IBM 1130]]. As such, the 2650 has a number of features that were common on 1960s [[minicomputer]]s, but rarely found on newly designed microprocessors of the 1970s. Among these, for instance, were processor status bits that were used to track the status of [[input/output]] devices, which makes it simpler to write interfacing code.<ref name=shack>{{cite web |title=Signetics 2650: An IBM on a Chip |website=CPU Shack |date=16 October 2016 |url=http://www.cpushack.com/2016/10/16/signetics-2650-an-ibm-on-a-chip/}}</ref> Another mini-like feature was its use of [[vectored interrupt]]s, which allowed devices to call the correct [[interrupt handler]] code by putting its memory location on the data bus and then forcing an interrupt. This avoids the need to write a centralized interrupt handler that reads additional data from the bus, determines which [[device driver]] is being invoked and then calls it; the 2650 can jump directly to the correct code, potentially stored on the device itself.

The 2650's [[processor register]]s were divided into sets, with a single global register R0 used as the [[Accumulator (computing)|accumulator]], and two sets of three [[index register]]s, both named R1, R2 and R3, for a total of seven registers.{{sfn|Rowe|1976}} For clarity, the second set was sometimes referred to as R1', R2' and R3' ("prime"). At any one time, one of the two sets of indexes were visible to the CPU. Which set was visible was controlled by a bit in the [[status register]], PSW. One could easily switch between the two sets of registers with a single instruction.<ref name=world>{{cite web |website=CPU World |title= Signetics 2650 family |url=https://www.cpu-world.com/CPUs/2650/index.html |date=11 February 2014 }}</ref> This allowed rapid switching of values during subroutine calls, [[operating system]] switches, or handling interrupts. Unlike the 1130, the registers were only 8-bit wide rather than 16-bit, but there were two sets in the 2650 rather than one in the 1130.<ref name=shack/>

Another of its mini-like features was the extensive support for [[indirect addressing]] on most instructions. Many instructions require data to be read from a location in memory, in most CPUs of the era that would be a single byte of data that is stored in memory referred to by a 16-bit location. In the 2650, the high-bit of that 16-bit location indicated indirection, meaning that the data was not located at this location in memory, but the one encoded in the remaining 15 bits of the address.<ref name=world/> This style of access allowed blocks of data to be more easily accessed than in systems that provided indirection solely through special instructions or index registers. One could step through memory by incrementing the address value stored in that single location in memory. This also resulted in considerable numbers of math instructions being applied to addresses, and to improve the performance of these operations, the 2650 included a second [[arithmetic logic unit]] just for address calculations.{{sfn|Rowe|1976}}

The downside to this approach was that the high-bit was no longer part of the address, meaning the [[address space]] was only 15 bits, and the machine could access only a total of 32 KB of memory. The address space was further limited by the use of another two bits of the address to indicate the indexing mode for all logical and arithmetic (i.e. non-branch) instructions. These bits controlled functions like whether the address should be post-incremented or pre-decremented, which is extremely useful for constructing loops. But with all of these bits already accounted for, only 13 were available for addresses in these instructions, meaning only 8 KB could be addressed directly. This meant the main memory was broken up as four 8 KB blocks.{{sfn|Rowe|1976}} To access memory outside the 8 KB where the instruction was located, the data bytes being pointed to had to contain an indirect address, pointing to some other location in memory.<ref name=world/> Doing so forced another memory read cycle, slowing performance.

When the 2650 was designed in 1972, these limitations on address space were not significant due to the small size and high cost of the [[static RAM]] memory typically used with these processors. At the time, machines typically contained 2 or 4 KB of RAM. But with the increasing use of [[dynamic RAM]] from the mid-1970s, machines with 8 and 16 KB of RAM, and ultimately 64 KB, became common and the addressing system on the 2650 became a significant hindrance.

The 2650 also contained an on-die [[call stack]], rather than the more common solution that sets aside a location in memory to hold the stack. The [[stack pointer]] was held in three bits in the PSW. An on-die stack is much faster, as the data can be accessed directly without waiting for it to be read from external memory, but it also takes up room on the die and is always limited in size as a result of practical tradeoffs. In the 2650, the return address stack was eight 15-bit entries deep.{{sfn|Rowe|1976}} This allowed programs to nest subroutines to eight levels.

While there were nine different [[addressing mode]]s, the lack of 16-bit registers and the 13–15-bit address space prevented widespread use. Despite this, an [[operating system]] ("2650 DOS")<ref>[https://ztpe.nl/2650/software/disk-operating-system/ 2650 DOS]</ref> was available, along with 8 KB and 12 KB [[BASIC]] interpreters (sold by Central Data Corporation USA), and many games of the ''[[Hunt the Wumpus]]'' style. Most programs were written in [[assembly language]].

==Uses==
[[File:Locale_RS6_Signetics PC1001.jpg|thumb|right|PC1001 evaluation board]]

Signetics sold 2650-based [[microprocessor development board]]s, first the PC1001<ref>Signetics Technical Note SP50; 2650 evaluation printed circuit board level system PC1001</ref><ref>Signetics Technical Note SS50; PC1001 monitor program "PIPBUG"</ref> and then its successor, the PC1500 "Adaptable Board Computer", ranging in price from A$165 to A$400. The chip by itself sold for around A$20. Several hardware construction projects and programming articles were published in magazines such as ''[[Electronics Australia]]'' and ''[[Elektor]]'' and related kits were sold by electronics stores. These factors led to its use by a number of [[hobby]]ists in many countries such as Australia, U.S.A.,<ref>Build a 2650 Microcomputer system, Radio Electronics magazine: April, May, June 1977</ref> United Kingdom, the Netherlands<ref>[[Hobby Computer Club]] (HCC) 2650 user group</ref> and Germany.<ref>Programmierbeispiele mit dem Mikroprozessor 2650, Johann Hatzenbichler, 1978 {{oclc|74475572}}</ref>

Two types of [[video game console]] used the Signetics 2650 or 2650A. The first group of consoles are based on the [[Signetics 2636]] [[video display controller]]; the [[Interton Video Computer 4000]] (1978) and variants of the [[1292 Advanced Programmable Video System]] (1979) belong to this group. The second group of consoles were based on the [[Signetics 2637]] as a [[video display controller]]; [[Emerson Radio|Emerson]] [[Arcadia 2001]] which was released in 1982 and which used a Signetics 2650 running at 0.895 [[Hertz|MHz]] as a [[Central processing unit|CPU]] belong to this group together with many other ones software-compatible (Leonardo, [[Hanimex]] MPT-03 etc.).<ref>{{cite web |url=https://www.digitpress.com/the_digs/arcadia/texts/2001-faq.htm#warning |title=Arcadia 2001: Frequently Asked Questions |date=4 June 2002 |access-date=26 December 2023 |first=Ward |last=Sharke |display-authors=etal |others=See "Credits and contributions" section for authors.}}</ref>

[[File:Locale_RS6_Photo Aug 31, 10 32 33 PM.jpg|thumb|Signetics 2650 Microprocessor Kit]]

At least six coin-operated video games were released in the 1970s which used the 2650 CPU: [[Atari, Inc.|Atari's]] ''[[Quiz Show (video game)|Quiz Show]]'', Meadows Games ''3D Bowling'', ''Gypsy Juggler'' and ''Lazer Command'', [[Cinematronics]] ''Embargo'', and a 1978 clone of ''[[Space Invaders]]'' by Italian company [[Zaccaria (company)|Zaccaria]] called ''The Invaders'' (the original by [[Taito]] uses an [[Intel 8080]] CPU). At least two coin-operated video games were released in the 1980s using the 2650. ''[[Hunchback (video game)|Hunchback]]'', and ''[[Hunchback Olympic]]''.

Zaccaria also released 28 pinball machines based on the 2650 CPU. Their successor company, MrGame, released four additional pinball machines using the 2650. Zaccaria seems to have licensed its design to Technoplay as well, and several more pinball machines were released using variations of Zaccaria circuit board designs.

The processor was also used in the [[Signetics Instructor 50]], which was a small computer designed to teach the use and programming of the 2650 CPU.

The 2650 was also used in some large items of equipment such as the Tektronix 8540, a microprocessor software development system which supported various [[in-circuit emulator]], trace memory and logic analyser cards for real-time debugging of microprocessor systems, as practiced in the 1980s. The 2650 provided the base operating system functions, data transfer, and interface to a host computer or serial computer terminal.

The processor was most suited as a microcontroller, due to its extensive I/O support:

* Single bit i/o pins on the processor (sense/flag bits)
* Signals to directly address two 8-bit I/O ports (control and data ports) using single byte instructions ([[Port I/O|port i/o]]). This circumvented the elaborate hardware other systems needed for [[memory-mapped I/O]]
* Signals to address another 256 I/O ports using an 8-bit address and two byte instructions, again, limiting the amount of hardware (address decoding) required. Philips emphasized this use as a micro-controller with a demonstration program showing the 2650 controlling an intelligent elevator system. Also, at trade fairs they showed the 2650 controlling a miniature 'sort and stack' robot

==Industrial Microcomputer System – IMS==
[[File:Locale_RS6_IMS001b.jpg|thumb|Philips IMS 2650 Eurocard computer system]]
For a short time starting 1979, Philips sold a modular 2650 computer called the 'IMS'{{snd}} Industrial Microcomputer System,<ref>Industrial Microcomputer System; System Specification, Philips Electronic Components and materials, 1980</ref> based on the [[Eurocard (printed circuit board)|Eurocard]] format in a 19" rack. It included [[CPU]], PROM, [[Random-access memory|RAM]], input, output and teletype modules. This system was meant as a more intelligent [[programmable logic controller]]. For development, they later added DEBUG, DISPLAY, INTERRUPT and MODEST ((E)PROM programmer) modules.

==Architecture==
The 2650 was supplied in a 40 pin plastic or ceramic [[Dual in-line package|DIL]] enclosure. An external single phase clock signal and a single 5V supply were needed.

The 2650 had many unusual features when compared to other microprocessors of the time:

*It was a fully static NMOS 8-bit microprocessor. The static nature was unusual for the time, and meant that the processor could be halted simply by stopping the clock signal. Programmers made grateful use of this feature to "single step' through a program using a push-button switch to generate the clock pulses.
*Unique was the 8-level 15-bit wide stack for the subroutine and interrupt return addresses which was integrated into the processor. The stack pointer used 3 bits of the upper status register. This meant subroutines and interrupts could only be nested 8 levels deep.
*The processor had only 13 real address lines, a further 2 address lines were connected to a 2-bit 'page register', resulting in a 32 KB address space. The page register was set when an absolute (direct) branch instruction, which used a full 15-bit address, was executed. All logical and arithmetic instructions used a 13-bit address augmented by the contents of the page register, thereby limiting their scope to an 8 KB page. These 2 upper address lines were also used (multiplexed) to select the appropriate I/O port during I/O operations (Control port, Data port or Extended port).
*Although the 2650 had only one interrupt input, this was a 'vectored' interrupt – the interrupting device needed to put a zero-relative displacement on the data bus, that would be used as the operand of a ZBSR (zero branch to subroutine relative) instruction to branch to the specified interrupt routine. Therefore, using indirect addressing, a maximum of 30 interrupt vectors could be stored in the first 64 bytes of memory. (The first three bytes were needed to hold an unconditional branch to the 'reset' routine). This vectored interrupt is also reminiscent of the [[PDP-11]] [[minicomputer]].

==Instruction set==
Although the 2650 is basically an 8-bit microprocessor, up to three bits of the addresses were also used with the 8-bit instruction to form longer opcodes. 64 opcodes are 9-bits long, and another 32 opcodes are 11-bit. Of the remaining 128 8-bit opcodes, 124 (126 in the 2650B) are implemented, giving a total of 444 (446) instructions.

Many more instructions are available as the behavior of the standard instructions can be modified by setting or clearing status bits: WC (with or without carry) and COM (logical or arithmetic compare). This doubled the number of rotate, add, subtract and compare instructions.

The instruction set is strongly [[orthogonal instruction set|orthogonal]]: all logic and arithmetic instructions can use all nine addressing modes:

* register
* immediate
* PC relative and PC relative indirect
* absolute and absolute indirect
* absolute indexed, absolute indexed with auto-increment, and absolute indexed with auto-decrement, both direct and indirect

The most significant bit of all relative and absolute addresses is used to indicate [[indirection]].

The only exceptions are where the opcodes of meaningless operations are used for other purposes:

* the opcode for AND register zero with register zero is used for the HALT instruction.
* the opcode for STORE register zero into register zero is used for the [[NOP (code)|NOP]] instruction.

Although the <code>LODZ R0</code> (load register zero with register zero) instruction is supported by the Signetics assembler, its binary encoding is not allowed. The assembler substitutes the binary for the semantically equivalent instruction <code>IORZ R0</code> instead.

===Indexing===
With all arithmetic and logical instructions using absolute (direct) addressing, bits 14 and 13 of the address field are used to indicate the indexing mode as follows:

* 00 no indexing
* 01 indexing with auto increment
* 10 indexing with auto decrement
* 11 indexing only

When indexing is specified, the register defined in the instruction becomes the index register, and the source/destination is implicitly Register zero. For indirect indexing, Post indexing is used, i.e. the indirect address is first fetched from memory and then the index is added to it.

===Branching===
Probably the most mini-computer like aspect of the 2650 is the enormous number (62) of branch (jump) instructions; all these instructions could also use indirection:

* BIRR and BIRA: Increment register and branch if non-zero (R0, R1, R2 or R3) with relative or absolute addressing
* BDRR and BDRA: Decrement register and branch if non-zero (R0, R1, R2 or R3) with relative or absolute addressing
* BRNR and BRNA: branch if register non-zero (R0, R1, R2 or R3) with relative or absolute addressing
* BCTR and BCTA: branch on condition True (zero, greater-than, less-than or unconditional) with relative or absolute addressing
* BCFR and BCFA: branch on condition False (zero, greater-than or less-than) with relative or absolute addressing.
* ZBRR: branch relative to address zero
* BXA: branch indexed

Like the [[Intel 8080]], the 2650 had instructions to conditionally branch to, and return from, a subroutine:

* BSTR and BSTA: branch to subroutine on condition True (zero, greater-than, less-than or unconditional) with relative or absolute addressing
* BSFR and BSFA: branch to subroutine on condition False (zero, greater-than or less-than) with relative or absolute addressing
* BSNR and BSNA: branch to subroutine if register non-zero (R0, R1, R2 or R3) with relative or absolute addressing
* RETC: return from subroutine on condition True (zero, greater-than, less-than or unconditional)
* RETE: return from interrupt on condition True (zero, greater-than, less-than or unconditional)
* ZBSR: branch to subroutine relative to address zero
* BSXA: branch to subroutine indexed

Only the branch instructions using absolute addressing used all 15 bits of the address field as address. Using such a branch instruction was, therefore, the only way to set the two bits in the page register (controlling bits 14 and 13 of the address bus) and changing the current 8 KB page.

==Versions==
* 2650 original version with 1.25 MHz maximum clock frequency
* 2650A improved version (minor fabrication changes to improve stability) 1.25 MHz maximum clock frequency
* 2650A-1 as 2650A with 2 MHz maximum clock frequency
* 2650B
* 2650B-1 as 2650B with 2 MHz maximum clock frequency

The 2650B had the following changes and improvements over the 2650A:<ref>Philips 2650 Series microprocessor short-form manual 02-1979; 9398 209 50011</ref>

* Two new signals{{snd}} "Bus Enable" on pin 15 and "Cycle Last" on pin 25, which marks the instruction fetch cycle.<ref>[https://ztpe.nl/2650/2650b/ 2650B]</ref>
* Program Status Word Upper bits 3 and 4 are settable and testable user flags (unused on the 2650A).
* Two new instructions STPL and LDPL to save and restore the lower status register from memory in order to simplify interrupt processing.
* Single byte register R0 instructions execute faster (one cycle rather than two).

==Second sources==
[[File:Locale_RS6_KL Philips MAB2650.jpg|thumb|right|Philips MAB2650A]]
In 1975, Signetics was sold to [[Philips]] and the 2650 was later incorporated into the [[NXP Semiconductors|Philips Semiconductors]] line. They made a version of the 2650 called the MAB2650A. Valvo, a subsidiary of Philips, sold the 2650 in Germany. Valvo also sold the VA200 single board (Eurocard) 2650 computer with 4 KB PROM/EPROM, 1 KB RAM and four I/O ports.<ref>VALVO VA 200 Mikrocomputer im Europa-Format: VALVO Applikationslaboratorium März 1978</ref>

Other producers of licensed copies of the chip were [[Harris Corporation|Harris]] and [[Intersil]].{{Citation needed|date=September 2025}}

==Peripheral chips==
The 2650 came with a full complement of peripheral chips:

* 2621 Video Encoder (PAL)
* 2622 Video Encoder (NTSC)
* 2636 Programmable Video Interface
* 2637 Universal Video Interface
* 2651 Programmable Communication Interface
* 2652 Multi-Protocol Communications Circuit (incl. Synchronous Data Link Control (SDLC))
* 2653 Polynomial Generator / Checker
* 2655 Programmable Peripheral Interface
* 2656 SMI (System memory interface)
* 2657 Direct Memory Access
* 2661 Enhanced Programmable Communication Interface (EPCI)
* 2670 Display Character and Graphics Generator
* 2671 Programmable Keyboard and Communications Controller
* 2672 Programmable Video Timing Controller
* 2673 Video Attributes Controller

Many of these peripheral chips were designed so they could also be used with other microprocessors, for example the datasheet of the [[SCN2672T|2672]] suggests using it with an [[Intel 8048]] [[microcontroller]].

Philips Technical Note 083 describes how to interface the 2651 PCI to various other microprocessors, such as the 8080, 8085, Z80, 8048 and 6800

Descendants of the 2651/2661 serial communications chips are still sold as the Philips SC26 series.

==2656 System Memory Interface==
The 2656 was specifically designed to augment, and interface with, the 2650 and make a 2-chip computer possible. It contained everything the 2650 lacked to make a complete computer:<ref>2650PC-4000 memory interface emulator using PROM's and FPLA's</ref>

* 2 KB 8-bit mask-programmed ROM program memory
* 128 bytes 8-bit RAM memory
* Clock generator with crystal or RC network
* Power-on reset
* Eight general purpose I/O pins

The I/O pins could be used as an 8-bit I/O port or programmed to generate enable signals for extra RAM, ROM or I/O ports. This was achieved by mask-programming a [[Programmable logic array|Programmable Logic Array]] in the 2656.

To develop and test the design before committing it to production, Philips sold the PC4000, a 2656 emulator board using PROMs and FPLAs to emulate the ROM and PLA in the 2656.

==Notes==
{{notelist}}

==References==
===Citations===
{{Reflist|2}}

===Bibliography===
* {{cite magazine |title=The Signetics 2650 |first=Jamieson |last=Rowe |magazine=Electronics Australia |date=September 1976 |url=http://messui.polygonal-moogle.com/comp/2650.pdf }}

== External links ==
* [https://amigan.1emu.net/releases/#amiarcadia 2650 Emulators]
* [http://datasheets.chipdb.org/Signetics/2650/2650UM.pdf Datasheet]
* [http://www.cpu-world.com/CPUs/2650/ Signetics 2650 family] CPU World
* [https://www.old-computers.com/museum/computer.asp?c=1029&st=1 Instructor 50] Old-computers.com
* [http://www.decodesystems.com/help-wanted/signetics-board.html Adaptable Board Computer] development system complete with 1 KiB PipBug [[Machine code monitor|monitor]] and 512 bytes of [[Random-access memory|RAM]]
* [https://web.archive.org/web/20110717055810/http://www.cpu-museum.com/2650_e.htm the 2650 at www.cpu-museum.com] (archived)
* [http://yesterdaystechnology.com/html/2650.html Electronics Australia 2650 board] at yesterdaystechnology.com
* [http://www.cpushack.com/2016/10/16/signetics-2650-an-ibm-on-a-chip/ Signetics 2650: An IBM on a Chip] retrospective at The CPUSHACK Museum (October 16, 2016)
* [https://www.arcade-museum.com/game_detail.php?game_id=8202 Zaccaria] The Invaders at Museum of the Game
* A 2650 cross assembler is available from https://shop-pdp.net/index.php
{{NXP Semiconductors}}

[[Category:Early microcomputers]]
[[Category:NXP Semiconductors]]
[[Category:8-bit microprocessors]]

Signetics 2650 - Revision history

RS-485: Imported from Wikipedia (overwrite)