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{{Short description|Electronic communication subsystem on an integrated circuit}}
{{Use American English|date=October 2018}}

{{Network science}}

A '''network on a chip''', or '''network on chip''' ('''NoC''' {{IPAc-en|ˌ|ɛ|n|ˌ|oʊ|ˈ|s|iː}} {{respell|en|oh|SEE}} or {{IPAc-en|n|ɒ|k}} {{respell|knock}}),<ref group="nb">This article uses the convention that "NoC" is pronounced {{IPAc-en|n|ɒ|k}} {{respell|nock}}. Therefore, it uses the convention "a" for the [[indefinite article]] corresponding to NoC ("'''a''' NoC"). Other sources may pronounce it as {{IPAc-en|ˌ|ɛ|n|ˌ|oʊ|ˈ|s|iː|}} {{respell|en|oh|SEE}} and therefore use "'''an''' NoC".</ref> is a [[Network theory|network]]-based [[communications subsystem]] on an [[integrated circuit]] ("chip"), most typically between [[System on a chip#Functional components|modules]] in a [[system on chip]] (SoC). The modules on the IC are typically semiconductor [[IP core]]s schematizing various functions of the [[computer system]], and are designed to be [[Modularity (networks)|modular]] in the sense of [[network science]]. The network on chip is a [[Router (computing)|router]]-based [[packet switching]] network between SoC [[Modularity|modules]].

NoC technology applies the theory and methods of [[computer networking]] to on-chip [[Communication#Computer|communication]] and brings notable improvements over conventional [[Bus (computing)|bus]] and [[Crossbar switch|crossbar]] [[Network architecture|communication architectures]]. Networks on chip come in many [[network topologies]], many of which are still experimental as of 2018. {{Citation needed|date=August 2022}}

In 2000s, researchers had started to propose a type of on-chip interconnection in the form of [[packet switching]] networks<ref>{{Cite book |last1=Guerrier |first1=P. |last2=Greiner |first2=A. |title=Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537) |chapter=A generic architecture for on-chip packet-switched interconnections |date=2000 |location=Paris, France |publisher=IEEE Comput. Soc |pages=250–256 |doi=10.1109/DATE.2000.840047 |isbn=978-0-7695-0537-4 }}</ref> in order to address the scalability issues of [[Bus (computing)|bus]]-based design. Preceding researches proposed the design that routes data packets instead of routing the wires.<ref>{{Cite book |title=Proceedings, 2001 Design Automation Conference : 38th DAC: Las Vegas Convention Center, Las Vegas, NV, June 18-22, 2001. |date=2001 |publisher=Association for Computing Machinery |others=Association for Computing Machinery, ACM Special Interest Group on Design Automation |isbn=1-58113-297-2 |location=New York, N.Y. |oclc=326240184}}</ref> Then, the concept of "networks on chip" was proposed in 2002.<ref>{{Cite journal |last1=Benini |first1=L. |last2=De Micheli |first2=G. |date=January 2002 |title=Networks on chips: a new SoC paradigm |journal=Computer |volume=35 |issue=1 |pages=70–78 |doi=10.1109/2.976921 |bibcode=2002Compr..35a..70B }}</ref> NoCs improve the [[scalability]] of systems-on-chip and the [[power efficiency]] of complex SoCs compared to other communication subsystem designs. They are an [[emerging technology]], with projections for large growth in the near future as [[multicore]] computer architectures become more common.

== Structure ==
{{Expand section|date=October 2018}}
NoCs can span synchronous and asynchronous clock domains, known as [[clock domain crossing]], or use unclocked [[asynchronous circuit|asynchronous]] logic. NoCs support [[Globally asynchronous locally synchronous|globally asynchronous, locally synchronous]] electronics architectures, allowing each [[processor core]] or functional unit on a system on chip to have its own [[clock domain]].<ref name=":02">{{Cite book|title=Network-on-chip: the Next Generation of System-on-Chip Integration|last1=Kundu|first1=Santanu|last2=Chattopadhyay|first2=Santanu|publisher=CRC Press|year=2014|isbn=978-1-4665-6527-2|edition=1st|location=Boca Raton, FL|page=3|oclc=895661009}}</ref>

== Architectures ==
{{Expand section|date=October 2018}}
NoC architectures typically model [[Sparsity|sparse]] [[small-world network]]s (SWNs) and [[scale-free network]]s (SFNs) to limit the number, length, area and [[power consumption]] of interconnection wires and [[Point-to-point (telecommunications)|point-to-point]] connections.

== Topology ==
The topology determines the physical layout and connections between nodes and channels. The message traverses hops, and each hop's channel length depends on the topology. The topology significantly influences both [[Latency (engineering)|latency]] and power consumption. Furthermore, since the topology determines the number of alternative paths between nodes, it affects the network traffic distribution, and hence the [[network bandwidth]] and performance achieved.<ref>{{Cite web |last=Staff |first=E. D. N. |date=2023-07-26 |title=Network-on-chip (NoC) interconnect topologies explained |url=https://www.edn.com/network-on-chip-noc-interconnect-topologies-explained/ |access-date=2023-11-17 |website=EDN |language=en-US}}</ref>

==Benefits ==
Traditionally, ICs have been designed with dedicated [[Point-to-point (telecommunications)|point-to-point]] connections, with one wire dedicated to each signal. This results in a [[Dense network|dense network topology]]. For large designs, in particular, this has several limitations from a [[Integrated circuit design|physical design]] viewpoint. It requires [[Power consumption|power]] [[Quadratic function|quadratic]] in the number of interconnections. The wires occupy much of the [[Die (integrated circuit)|area of the chip]], and in [[nanometer]] [[CMOS]] technology, interconnects dominate both performance and dynamic [[power dissipation]], as signal propagation in wires across the chip requires multiple [[clock cycle]]s. This also allows more [[parasitic capacitance]], [[Parasitic element (electrical networks)|resistance and inductance]] to accrue on the circuit. (See [[Rent's rule]] for a discussion of wiring requirements for point-to-point connections).

[[Sparse network|Sparsity]] and [[Locality of reference|locality]] of interconnections in the communications subsystem yield several improvements over traditional [[Bus (computing)|bus]]-based and [[Crossbar switch|crossbar]]-based systems.

{{Clear}}

==Parallelism and scalability==
The wires in the links of the network-on-chip are shared by many [[signals]]. A high level of [[Parallel computing|parallelism]] is achieved, because all [[data link]]s in the NoC can operate simultaneously on different [[Packet switching|data packets]].{{Why?|date=October 2018}} Therefore, as the complexity of [[Very-large-scale integration|integrated systems]] keeps growing, a NoC provides enhanced performance (such as [[throughput]]) and [[scalability]] in comparison with previous communication architectures (e.g., dedicated point-to-point signal [[wire]]s, shared [[Bus (computing)|buses]], or segmented buses with [[Network bridge|bridges]]). The [[algorithm]]s{{Which|date=October 2018}} must be designed in such a way that they offer [[Massively parallel|large parallelism]] and can hence utilize the potential of NoC.

==Current research==
[[File:Locale_RS6_Wireless TSV (model).PNG|thumb|WiNoC in the 3D-chiplet]]
Some researchers{{Who|date=June 2015}} think that NoCs need to support [[quality of service]] (QoS), namely achieve the various requirements in terms of [[throughput]], end-to-end delays, [[Fairness measure|fairness]],<ref>{{cite journal|title=Balancing On-Chip Network Latency in Multi-Application Mapping for Chip-Multiprocessors|journal=IPDPS|date=May 2014}}</ref> and [[Time limit|deadlines]].{{citation needed|date=June 2015}} Real-time computation, including audio and video playback, is one reason for providing QoS support. However, current system implementations like [[VxWorks]], [[RTLinux]] or [[QNX]] are able to achieve sub-millisecond real-time computing without special hardware.{{citation needed|date=June 2015}}

This may indicate that for many [[Real-time computing|real-time]] applications the service quality of existing on-chip interconnect infrastructure is sufficient, and dedicated [[hardware logic]] would be necessary to achieve microsecond precision, a degree that is rarely needed in practice for end users (sound or video jitter need only tenth of milliseconds latency guarantee). Another motivation for NoC-level [[quality of service]] (QoS) is to support multiple concurrent users sharing resources of a single [[chip multiprocessor]] in a public [[cloud computing]] infrastructure. In such instances, hardware QoS logic enables the service provider to make [[Service-level agreement|contractual guarantees]] on the level of service that a user receives, a feature that may be deemed desirable by some corporate or government clients.{{citation needed|date=June 2015}}

Many challenging research problems remain to be solved at all levels, from the physical link level through the network level, and all the way up to the system architecture and application software. The first dedicated research symposium on networks on chip was held at [[Princeton University]], in May 2007.<ref>[http://2007.nocsymposium.org/ NoCS 2007] {{Webarchive|url=https://web.archive.org/web/20080901221034/http://2007.nocsymposium.org/ |date=2008-09-01 }} website.</ref> The second [[IEEE]] International Symposium on Networks-on-Chip was held in April 2008 at [[Newcastle University]].

Research has been conducted on integrated [[optical waveguide]]s and devices comprising an optical network on a chip (ONoC).<ref>[https://archive.today/20120730164033/http://www.cl.cam.ac.uk/users/rdm34/onChipNetBib/browser.htm On-Chip Networks Bibliography]</ref><ref name="ONoC">{{Cite web |url=http://www.ece.ust.hk/~eexu/bibliography.html |title=Inter/Intra-Chip Optical Network Bibliography- |access-date=2015-07-02 |archive-date=2015-09-23 |archive-url=https://web.archive.org/web/20150923233005/http://www.ece.ust.hk/~eexu/bibliography.html |url-status=live }}</ref>

The possible way to increasing the performance of NoC is use wireless communication channels between [[chiplets]] — named wireless network on chip (WiNoC).<ref>Slyusar V. I., Slyusar D.V. Pyramidal design of nanoantennas array. // VIII International Conference on Antenna Theory and Techniques (ICATT'11). - Kyiv, Ukraine. - National Technical University of Ukraine "Kyiv Polytechnic Institute". - September 20–23, 2011. - Pp. 140–142. [https://slyusar.kiev.ua/ICATT_2011_Slyusar2.pdf] {{Webarchive|url=https://web.archive.org/web/20190717084106/http://slyusar.kiev.ua/ICATT_2011_Slyusar2.pdf|date=2019-07-17}}</ref>

==Side benefits==
In a multi-core system, connected by NoC, coherency messages and cache miss requests have to pass switches. Accordingly, switches can be augmented with simple tracking and forwarding elements to detect which cache blocks will be requested in the future by which cores. Then, the forwarding elements multicast any requested block to all the cores that may request the block in the future. This mechanism reduces cache miss rate.<ref name="Tree-based scheme for reducing shared cache miss
rate leveraging regional, statistical and temporal
similarities">{{Cite journal|url=https://ieeexplore.ieee.org/document/6695819|archive-url=https://web.archive.org/web/20181209212956/https://ieeexplore.ieee.org/document/6695819/|url-status=dead|archive-date=December 9, 2018|title=Tree-based scheme for reducing shared cache miss rate leveraging regional, statistical and temporal similarities|journal=IET Computers & Digital Techniques|volume=8|pages=30–48|author=Marzieh Lenjani |author2=Mahmoud Reza Hashemi |doi=10.1049/iet-cdt.2011.0066|year=2014|url-access=subscription}}</ref>

==Benchmarks==
NoC development and studies require comparing different proposals and options. NoC traffic patterns are under development to help such evaluations. Existing NoC benchmarks include NoCBench and MCSL NoC Traffic Patterns.<ref name="MCSL NoC Traffic Patterns">{{Cite web|url=http://www.ece.ust.hk/~eexu/traffic.html|title=NoC traffic|website=www.ece.ust.hk|access-date=2018-10-08|archive-date=2017-12-25|archive-url=https://web.archive.org/web/20171225203037/http://www.ece.ust.hk/~eexu/traffic.html|url-status=live}}</ref>

==Interconnect processing unit==
An interconnect processing unit (IPU)<ref>Marcello Coppola, Miltos D. Grammatikakis, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi, "Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC", CRC Press, 2008, {{ISBN|978-1-4200-4471-3}}</ref> is an on-chip communication network with [[computer hardware|hardware]] and [[software]] components which jointly implement key functions of different [[system-on-chip]] programming models through a set of communication and [[synchronization primitive]]s and provide [[low-level]] platform services to enable advanced features{{Which|date=October 2018}} in modern heterogeneous applications{{Definition needed|date=October 2018}} on a single [[Die (integrated circuit)|die]].

==See also==
*[[Arteris]]
*[[Electronic design automation]] (EDA)
*[[Integrated circuit design]]
* [[CUDA]]
*[[Globally asynchronous locally synchronous|Globally asynchronous, locally synchronous]]
*[[Network architecture]]

== Notes ==
{{Reflist|group=nb}}

== References ==
{{Reflist}}
Adapted from [http://www.ee.technion.ac.il/people/kolodny/ Avinoam Kolodny's] {{Webarchive|url=https://web.archive.org/web/20090110073554/http://www.ee.technion.ac.il/people/kolodny/ |date=2009-01-10 }}'s column in the ACM [http://www.sigda.org SIGDA] [https://web.archive.org/web/20070208034716/http://www.sigda.org/newsletter/index.html e-newsletter] by [http://www.eecs.umich.edu/~imarkov/ Igor Markov] {{Webarchive|url=https://web.archive.org/web/20120301131724/http://www.eecs.umich.edu/~imarkov/ |date=2012-03-01 }} <br />The original text can be found at http://www.sigda.org/newsletter/2006/060415.txt {{Webarchive|url=https://web.archive.org/web/20060925023243/http://www.sigda.org/newsletter/2006/060415.txt |date=2006-09-25 }}

== Further reading ==

* {{Cite book|title=Network-on-chip: the Next Generation of System-on-Chip Integration|last1=Kundu|first1=Santanu|last2=Chattopadhyay|first2=Santanu|publisher=CRC Press|year=2014|isbn=978-1-4665-6527-2|edition=1st|location=Boca Raton, FL|oclc=895661009}}
* {{Cite book|title=Networks-on-Chip: From Implementations to Programming Paradigms|publisher=Morgan Kaufmann|year=2014|isbn=978-0-12-801178-2|edition=1st|location=Amsterdam, NL|oclc=894609116|author=Sheng Ma |author2=Libo Huang |author3=Mingche Lai |author4=Wei Shi |author5=Zhiying Wang }}
* {{Cite book|title=Microarchitecture of Network-on-Chip Routers: A Designer's Perspective|author=Giorgios Dimitrakopoulos |author2=Anastasios Psarras |author3=Ioannis Seitanidis |isbn=978-1-4614-4301-8|location=New York, NY|oclc=890132032|edition=1st|date = 2014-08-27}}
* {{Cite book|title=On-chip Networks|author=Natalie Enright Jerger |author2=Tushar Krishna |author3=Li-Shiuan Peh |isbn=978-1-62705-996-1|edition=2nd|location=San Rafael, California|oclc=991871622|date = 2017-06-19}}
* {{Cite journal|url=https://ieeexplore.ieee.org/document/6695819|archive-url=https://web.archive.org/web/20181209212956/https://ieeexplore.ieee.org/document/6695819/|url-status=dead|archive-date=December 9, 2018|title=Tree-based scheme for reducing shared cache miss rate leveraging regional, statistical and temporal similarities|journal=IET Computers & Digital Techniques|volume=8|pages=30–48|author=Marzieh Lenjani |author2=Mahmoud Reza Hashemi |doi=10.1049/iet-cdt.2011.0066|year=2014|url-access=subscription}}

==External links==
* [http://async.org.uk/noc2006 DATE 2006 workshop on NoC] {{Webarchive|url=https://web.archive.org/web/20110719005724/http://async.org.uk/noc2006/ |date=2011-07-19 }}
* [http://2007.nocsymposium.org/ NoCS 2007 - The 1st ACM/IEEE International Symposium on Networks-on-Chip] {{Webarchive|url=https://web.archive.org/web/20080901221034/http://2007.nocsymposium.org/ |date=2008-09-01 }}
* [http://async.org.uk/nocs2008 NoCS 2008 - The 2nd IEEE International Symposium on Networks-on-Chip] {{Webarchive|url=https://web.archive.org/web/20071016104105/http://async.org.uk/nocs2008/ |date=2007-10-16 }}
* Jean-Jacques Lecler, Gilles Baillieu, ''Design Automation for Embedded Systems (Springer), "Application driven network-on-chip architecture exploration & refinement for a complex SoC", June 2011, Volume 15, Issue 2, pp 133–158, [[doi:10.1007/s10617-011-9075-5]] [Online] http://www.arteris.com/hs-fs/hub/48858/file-14363521-pdf/docs/springer-appdrivennocarchitecture8.5x11.pdf''

{{System on a chip}}
{{Processor technologies}}
{{Hardware acceleration}}

[[Category:Network on a chip| ]]
[[Category:Electronic design automation]]
[[Category:Integrated circuits]]
[[Category:System on a chip]]
[[Category:Hardware acceleration]]
[[Category:Network theory]]
[[Category:Computer networking]]
[[Category:Parallel computing]]
[[Category:Communication circuits]]
[[Category:Modularity]]

Network on a chip - Revision history

RS-485: Imported from Wikipedia (overwrite)