RS-485: Imported from Wikipedia (overwrite)

2026-05-02T19:05:33Z

Imported from Wikipedia (overwrite)

New page

{{Short description|Processor interconnect bus}}
The '''Intel Ultra Path Interconnect''' ('''UPI''')<ref name="Intel QPI">{{cite web |title= Intel® Xeon® Processor Scalable Family Technical Overview|date= September 14, 2017 |publisher= Intel Corporation |url= https://software.intel.com/en-us/articles/intel-xeon-processor-scalable-family-technical-overview|author=David Mulnix|access-date= September 17, 2017 }}</ref><ref>{{cite web|url=https://www.tomshardware.com/reviews/intel-xeon-platinum-8176-scalable-cpu,5120-4.html|title=The Mesh Topology & UPI - Intel Xeon Platinum 8176 Scalable Processor Review|date=11 July 2017}}</ref> is a scalable [[microprocessor|processor]] [[Electrical connection|interconnect]] developed by [[Intel]] which replaced the [[Intel QuickPath Interconnect]] (QPI) in [[Xeon]] [[Skylake-SP]] platforms starting in 2017.

==Interconnect==
UPI is a [[low-latency]] [[memory coherence|coherent]] interconnect for scalable [[multiprocessor]] systems with a shared [[address space]]. It uses a [[Cache coherence#Directory-based|directory-based]] home [[bus snooping|snoop]] coherency protocol. Data on the UPI bus can be transferred in both directions simultaneously. Transfer speed of UPI 2.0 link reaches 24 [[GT/s]] (48 GB/s per direction per link). Supporting processors typically have two or three UPI links.

Comparing to QPI, it improves power efficiency with a new low-power state, improves transfer efficiency with a new packetization format, and improves scalability with protocol layer that does not require preallocation of resources.

UPI only supports directory-based coherency, unlike previous QPI processors which supported multiple snoop modes (no snoop, early snoop, home snoop, and directory).

A combined caching and home agent (CHA) handles resolution of coherency across multiple processors, as well as snoop requests from processor cores and local and remote agents. Separate physical CHAs are placed within each processor core and [[CPU cache|last level cache (LLC)]] bank to improve scalability according to the number of cores, memory controllers, or the sub-[[Non-uniform memory access|NUMA]] clustering mode. The address space is interleaved across different CHAs, which act like a single logical agent.

==See also==
* [[HyperTransport]]
* [[Front-side bus]]

==References==
{{Reflist}}

==External links==
* [https://software.intel.com/en-us/articles/intel-xeon-processor-scalable-family-technical-overview Intel® Xeon® Processor Scalable Family Technical Overview]

{{Intel technology}}
{{Computer-bus}}

{{DEFAULTSORT:Intel UltraPath Interconnect}}
[[Category:Computer buses]]
[[Category:Intel products|UltraPath Interconnect]]
[[Category:Serial buses]]

Intel Ultra Path Interconnect - Revision history

RS-485: Imported from Wikipedia (overwrite)