RS-485: Imported from Wikipedia (overwrite)

2026-05-02T18:00:28Z

Imported from Wikipedia (overwrite)

New page

{{Short description|Microprocessor architecture}}
{{POWER, PowerPC, and Power ISA}}
'''CoreConnect''' is a [[microprocessor]] [[Bus (computing)|bus]]-architecture from [[IBM]] for [[system-on-a-chip]] (SoC) designs. It was designed to ease the integration and reuse of processor, system, and peripheral [[Multi-core (computing)|cores]] within standard and custom SoC designs. As a standard SoC [[design point]], it serves as the foundation of IBM or non-IBM devices. Elements of this architecture include the processor local bus (PLB), the on-chip peripheral bus (OPB), a bus bridge, and a [[device control register]] (DCR) bus. High-performance peripherals connect to the high-[[Bit rate|bandwidth]], low-[[Latency (engineering)|latency]] PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB. CoreConnect has bridging capabilities to the competing [[Advanced Microcontroller Bus Architecture|AMBA]] bus architecture, allowing reuse of existing SoC-components.

IBM makes the CoreConnect bus available as a no-fee, no-royalty architecture to tool-vendors, core IP-companies, and chip-development companies. As such it is licensed by over 1500 electronics companies such as [[Cadence Design Systems|Cadence]], [[Ericsson]], [[Lucent]], [[Nokia]], [[Siemens]] and [[Synopsys]].

The CoreConnect is an integral part of IBM's embedded offerings and is used extensively in their [[PowerPC 400|PowerPC 4x0]] based designs. In the past, [[Xilinx]] was using CoreConnect as the infrastructure for all of their embedded processor designs.

== Processor Local Bus (PLB) ==
*General processor local bus
*Synchronous, nonmultiplexed bus
*Separate Read, Write data buses
*Supports concurrent Read, Writes
*Multimaster, programmable-priority, arbitrated bus
*32-bit up to 64-bit address
*32-/64-/128-bit implementations (to 256-bit)
*66/133/183 MHz (32-/64-/128-bit)
*Pipelined, supports early split transactions
*Overlapped arbitration (last cycle)
*Supports fixed, variable-length bursts
*Bus locking
*High bandwidth capabilities, up to 2.9 [[Gigabyte|GB]]/s.

== On-chip Peripheral Bus (OPB) ==
*Peripheral bus for slower devices
*Synchronous, nonmultiplexed bus
*Multimaster, arbitrated bus
*Up to a 64-bit address bus
*Separate 32-bit Read, Write buses
*Pipelined transactions
*Overlapped arbitration (last cycle)
*Supports bursts
*Dynamic bus sizing, 8-, 16-, 32-bit devices
*Single-cycle data transfers
*Bus locking (parking)

== Device Control Register (DCR) bus ==

This bus:

* provides fully [[Synchronization (computer science)|synchronous]] movement of [[Processor register|GPR]] data between [[Central processing unit|CPU]] and slave logic
* functions as a synchronous, nonmultiplexed bus
* has separate buses to read and to write data
* consists of a single-master, multiple-slave bus
* includes a 10-bit address bus
* features 32-bit data buses
* uses two-cycle minimum Read/Write cycles
* utilizes distributed multiplexer architecture
* supports 8-, 16-, and 32-bit devices
* performs single-cycle data transfers

== External links ==
* [https://web.archive.org/web/20090129183058/http://www-01.ibm.com/chips/techlib/techlib.nsf/products/CoreConnect_Bus_Architecture CoreConnect bus architecture, IBM.com]
* [https://web.archive.org/web/20040616075914/http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=dr_pcentral_coreconnect CoreConnect Technology, Xilinx.com]
* [https://web.archive.org/web/20071021093848/http://www-03.ibm.com/technology/ges/semiconductor/power/licensing/coreconnect/crcon_ugl.html CoreConnect licensing, IBM.com]
* [https://web.archive.org/web/20160303185318/http://electronicdesign.com/Articles/Index.cfm?AD=1&ArticleID=4089 CoreConnect: The On-Chip Bus System, ElectronicDesign.com]
* [https://web.archive.org/web/20110520034719/https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/2F9323ECBC8CFEE0872570F4005C5739/%24file/DcrBus.pdf Device Control Register Bus 3.5 Architecture Specifications]

{{Computer-bus}}

[[Category:Computer buses]]
[[Category:IBM computer hardware]]

CoreConnect - Revision history

RS-485: Imported from Wikipedia (overwrite)