https://rs-485.com/index.php?action=history&feed=atom&title=Bit-serial_architectureBit-serial architecture - Revision history2026-05-04T00:53:37ZRevision history for this page on the wikiMediaWiki 1.42.3https://rs-485.com/index.php?title=Bit-serial_architecture&diff=2268&oldid=prevAdmin: Imported missing template from Wikipedia2026-05-03T16:52:40Z<p>Imported missing template from Wikipedia</p>
<p><b>New page</b></p><div>{{Short description|Computational system in which data are sent one bit at a time down a wire}}<br />
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{{Use list-defined references|date=November 2022}}<br />
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In [[computer architecture]], '''bit-serial architectures''' send data one bit at a time, along a single wire, in contrast to [[Parallel transmission|bit-parallel]] [[word (computer architecture)|word]] architectures, in which data values are sent all bits or a word at once along a group of wires. <br />
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All digital computers built before 1951, and most of the early [[massively parallel|massive parallel processing]] machines used a bit-serial architecture—they were [[serial computer]]s.<br />
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Bit-serial architectures were developed for [[digital signal processing]] in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation.<ref name="Denyer_1995"/><br />
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The [[HP Nut]] processor used in many [[Hewlett-Packard calculator]]s operated bit-serially.<ref name="Smith_2023"/><br />
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Assuming ''N'' is an arbitrary integer number, ''N'' serial processors will often take less [[Field-programmable gate array|FPGA]] area and have a higher total performance than a single ''N''-bit parallel processor.<ref name="Andraka"/><br />
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==See also==<br />
* [[Serial computer]]<!-- with possibilities --><br />
* [[1-bit computing]]<br />
* [[Bit banging]]<br />
* [[Bit slicing]]<br />
* [[BKM algorithm]]<br />
* [[CORDIC]]<br />
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==References==<br />
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<ref name="Denyer_1995"><br />
{{cite book |title=VLSI signal processing: a bit-serial approach |series=VLSI systems series |author-first1=Peter B. |author-last1=Denyer |author-link1=Peter B. Denyer |author-first2=David |author-last2=Renshaw |publisher=[[Addison-Wesley]] |date=1985 |isbn=978-0-201-13306-6 |url=https://books.google.com/books?id=EklTAAAAMAAJ}}</ref><br />
<ref name="Andraka">{{cite web |title=Building a High Performance Bit Serial Processor in an FPGA |author-first=Raymond J. |author-last=Andraka. |url=http://www.fpga-guru.com/files/supercn.pdf}}</ref><br />
<ref name="Smith_2023">{{cite web |title=HP-15C CE woes: 1 bug, 2 limitations, 3 questions |author-first=Eric L. "brouhaha" |author-last=Smith |date=2023-08-09 |work=MoHPC - The Museum of HP Calculators |url=https://www.hpmuseum.org/forum/thread-20281.html |access-date=2023-09-24 |url-status=live |archive-url=https://web.archive.org/web/20230810144726/https://www.hpmuseum.org/forum/thread-20281.html |archive-date=2023-08-10}}</ref><br />
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==External links==<br />
* [http://portal.acm.org/citation.cfm?id=503063 Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method]<br />
* [http://portal.acm.org/citation.cfm?id=741014 BIT-Serial FIR filters with CSD Coefficients for FPGAs]<br />
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{{CPU technologies}}<br />
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[[Category:Data transmission]]<br />
[[Category:Serial computers]]<br />
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