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{{short description|Possible future digital logic technologies}}
{{Update|date=December 2024}}
'''Beyond CMOS''' refers to the possible future [[digital logic]] technologies beyond the [[MOSFET#Scaling|scaling limits]] of [[CMOS]] technology.<ref name=Hut2002>{{Cite web |url=https://web.stanford.edu/class/ee311/NOTES/Hutchby_ProcIEEE03.pdf |title=Extending the road beyond CMOS. Hutchby 2002 |access-date=2023-04-16 |archive-date=2022-12-06 |archive-url=https://web.archive.org/web/20221206003711/http://web.stanford.edu/class/ee311/NOTES/Hutchby_ProcIEEE03.pdf |url-status=live }}</ref><ref name=NikonovYoung2012>{{cite arXiv |first1=Dmitri E. |last1=Nikonov |first2=Ian A. |last2=Young |eprint=1302.0244 |title=Overview of Beyond-CMOS Devices and A Uniform Methodology for Their Benchmarking |date=September 2012 |class=cond-mat.mes-hall }}</ref><ref name=Bern2010>{{cite journal |url=https://www.fp7-nanotec.eu/content/device-and-architecture-outlook-beyond-cmos-switches-kerry-bernstein-wolfgang-porod-and-jeff |title=Device and Architecture Outlook for Beyond CMOS Switches |author=Bernstein |year=2011 |display-authors=etal |access-date=2015-02-22 |archive-date=2015-02-22 |archive-url=https://web.archive.org/web/20150222223024/https://www.fp7-nanotec.eu/content/device-and-architecture-outlook-beyond-cmos-switches-kerry-bernstein-wolfgang-porod-and-jeff |url-status=live }}</ref><ref name=Carta>{{Cite web |url=http://www.mos-ak.org/dresden/publications/T4_Carta_MOS-AK_12.pdf |title=Review of Advanced and Beyond CMOS FET Technologies for Radio Frequency Circuit Design. Carta 2011 |access-date=2015-02-23 |archive-url=https://web.archive.org/web/20150223025752/http://www.mos-ak.org/dresden/publications/T4_Carta_MOS-AK_12.pdf |archive-date=2015-02-23 |url-status=dead }}</ref> which limits device density and speeds due to heating effects.<ref name=Frank2002>{{cite journal |first=D.J. |last=Frank |title=Power-constrained CMOS scaling limits |journal=IBM Journal of Research and Development |volume=46 |issue=2.3 |pages=235–244 |date=March 2002 |doi=10.1147/rd.462.0235 |citeseerx=10.1.1.84.4043}}</ref>

''Beyond CMOS'' is the name of one of the 7 focus groups in [[ITRS 2.0]] (2013) and in its successor, the [[International Roadmap for Devices and Systems]].

[[File:Clock CPU Scaling.jpg|thumb|CPU clock scaling|390x390px]]

CPUs using CMOS were released from 1986 (e.g. 12 MHz [[Intel 80386]]). As CMOS transistor dimensions were shrunk the clock speeds also increased. Since about 2004 CMOS CPU clock speeds have leveled off at about 3.5 GHz.

[[File:Beyond CMOS IRDS.jpg|thumb|A graph of efficiency gains possible under 'more Moore' (i.e., further improvements to current technology) and 'Beyond CMOS' (i.e., a paradigm shift in technology). From the International Roadmap for Devices and Systems<ref>{{cite web |series=The International Roadmap for Devices and Systems |edition=2017 |year=2018 |publisher=IEEE |title=Beyond CMOS |url=https://irds.ieee.org/images/files/pdf/2017/2017IRDS_BC.pdf |access-date=2018-07-03 |archive-date=2018-07-03 |archive-url=https://web.archive.org/web/20180703133249/https://irds.ieee.org/images/files/pdf/2017/2017IRDS_BC.pdf |url-status=live }}</ref>]]

CMOS devices sizes continue to shrink – see Intel's [[process–architecture–optimization model]] (and older [[tick–tock model]]) and [[International Technology Roadmap for Semiconductors|ITRS]]:
* [[22 nm process|22 nanometer]] [[Ivy Bridge (microarchitecture)|Ivy Bridge]] in 2012
* first [[14 nm process|14 nanometer]] processors shipped in Q4 2014.
* In May 2015, Samsung Electronics showed a 300 mm wafer of [[10 nm process|10 nanometer]] [[FinFET]] chips.<ref>{{cite web|title=Samsung vows to start 10nm chip production in 2016|url=http://www.kitguru.net/components/anton-shilov/samsung-vows-to-start-10nm-chip-production-in-2016-shows-first-wafers/|date=23 May 2015|accessdate=16 July 2015|archive-date=16 July 2015|archive-url=https://web.archive.org/web/20150716193300/http://www.kitguru.net/components/anton-shilov/samsung-vows-to-start-10nm-chip-production-in-2016-shows-first-wafers/|url-status=live}}</ref>

It is not yet clear if CMOS transistors will still work below [[3 nm process|3 nm]].<ref name=Carta/>

==Comparisons of technology==
About 2010 the [[Nanoelectronic Research Initiative]] (NRI) studied various circuits in various technologies.<ref name=NikonovYoung2012/>

Nikonov benchmarked (theoretically) many technologies in 2012,<ref name=NikonovYoung2012/> and updated it in 2014.<ref name=NY2014>{{cite journal |title=Benchmarking of Beyond-CMOS Exploratory – Devices for Logic Integrated Circuits |journal=IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |volume=1 |pages=3–11 |last1=Nikonov |last2=Young |year=2015 |doi=10.1109/JXCDC.2015.2418033 |bibcode=2015IJESS...1....3N |doi-access=free }}</ref> The 2014 benchmarking included 11 electronic, 8 [[spintronic]], 3 [[orbitronic]], 2 [[ferroelectric]], and 1 [[straintronics]] technology.<ref name=NY2014/>

The 2015 [[ITRS 2.0]] report included a detailed chapter on ''Beyond CMOS'',<ref name=ITRS-BC2015>{{cite book |url=https://www.dropbox.com/sh/3jfh5fq634b5yqu/AACxgvNR8zhcTYt2cp2nj0WOa/6_2015%20ITRS%202.0%20Beyond%20CMOS.pdf |series=International Technology Roadmap for Semiconductors 2.0 |edition=2015 |title=Beyond CMOS |access-date=2017-06-16 |archive-date=2023-04-16 |archive-url=https://web.archive.org/web/20230416232804/https://www.dropbox.com/sh/3jfh5fq634b5yqu/AACxgvNR8zhcTYt2cp2nj0WOa/6_2015%20ITRS%202.0%20Beyond%20CMOS.pdf |url-status=live }}</ref> covering RAM and logic gates.

==Some areas of investigation==
* [[Magneto-electric spin-orbit]] logic<ref>{{Cite journal |last1=Manipatruni |first1=Sasikanth |last2=Nikonov |first2=Dmitri E. |last3=Lin |first3=Chia-Ching |last4=Gosavi |first4=Tanay A. |last5=Liu |first5=Huichu |last6=Prasad |first6=Bhagwati |last7=Huang |first7=Yen-Lin |last8=Bonturim |first8=Everton |last9=Ramesh |first9=Ramamoorthy |last10=Young |first10=Ian A. |date=2018-12-03 |title=Scalable energy-efficient magnetoelectric spin–orbit logic |url=http://dx.doi.org/10.1038/s41586-018-0770-2 |journal=Nature |volume=565 |issue=7737 |pages=35–42 |doi=10.1038/s41586-018-0770-2 |pmid=30510160 |s2cid=256769872 |issn=0028-0836|url-access=subscription }}</ref>
* [[Tunnel junction]] devices, e.g. [[tunnel field-effect transistor]]<ref name="Seabaugh2013">{{cite journal |url=https://spectrum.ieee.org/the-tunneling-transistor |title=The Tunneling Transistor |journal=IEEE Spectrum |publisher=IEEE |date=September 2013 |author=Seabaugh |volume=50 |issue=10 |pages=35–62 |doi=10.1109/MSPEC.2013.6607013 |s2cid=2729197 |access-date=2023-04-16 |archive-date=2021-06-29 |archive-url=https://web.archive.org/web/20210629023724/https://spectrum.ieee.org/semiconductors/devices/the-tunneling-transistor |url-status=live |url-access=subscription }}</ref>
* [[Indium antimonide]] transistors
* [[carbon nanotube field-effect transistor|Carbon nanotube FET]], e.g. CNT [[tunnel field-effect transistor]]
* [[Graphene nanoribbons]]
* [[Molecular electronics]]
* [[Spintronics]] — many variants
* [[ARC Centre of Excellence in Future Low-Energy Electronics Technologies|Future low-energy electronics technologies]], ultra-low dissipation conduction paths, including:
**[[Topological insulator|Topological materials]]
**[[Polariton superfluid|Exciton superfluids]]
* [[Photonics]] and [[optical computing]]
* [[Superconducting computing]]
** [[rapid single flux quantum|Rapid single-flux quantum]] (RSFQ)

==Superconducting computing and RSFQ==

[[Superconducting computing]] includes several beyond-CMOS technologies that use superconducting devices, namely [[Josephson junctions]], for electronic signals processing and computing. One variant called [[rapid single flux quantum|rapid single-flux quantum]] (RSFQ) logic was considered promising by the NSA in a 2005 technology survey despite the drawback that available superconductors require [[Cryogenics|cryogenic]] temperatures. More energy-efficient superconducting logic variants have been developed since 2005 and are being considered for use in large scale computing.<ref name="Holmes2013">{{cite journal |last1=Holmes |first1=D.S. |last2=Ripple |first2=A.L. |last3=Manheimer |first3=M.A. |title=Energy-efficient superconducting computing—power budgets and requirements |journal=IEEE Trans. Appl. Supercond. |volume=23 |issue=3 |at=1701610 |date=June 2013 |doi=10.1109/TASC.2013.2244634 |bibcode=2013ITAS...2301610H |s2cid=20374012 }}</ref><ref name="Holmes2015">{{cite journal |last1=Holmes |first1=D.S. |last2=Kadin |first2=A.M. |last3=Johnson |first3=M.W. |title=Superconducting Computing in Large-Scale Hybrid Systems |journal=Computer |volume=48 |issue=12 |pages=34–42 |date=December 2015 |doi=10.1109/MC.2015.375 |bibcode=2015Compr..48l..34S |s2cid=26578755 }}</ref>

==See also==
* [[International Technology Roadmap for Semiconductors]]
* [[International Roadmap for Devices and Systems]]
* [[Moore's law]]
* [[MOSFET#Scaling|MOSFET scaling]]
* [[Nanostrain]], a project to characterise piezoelectric materials for low power switches
* [[S-PULSE]], the EU Shrink-Path of Ultra-Low Power Superconducting Electronics initiative
* Probabilistic complementary metal-oxide semiconductor ([[PCMOS]])

==References==
{{reflist}}

==Further reading==
* {{cite web |title=New Door in the "Beyond CMOS" World |author-first=Niloy |author-last=Banerjee |date=2019-09-03 |work=BISinfotech |url=https://www.bisinfotech.com/new-door-in-the-beyond-cmos-world/ |access-date=2022-05-13 |url-status=live |archive-url=https://web.archive.org/web/20220513194310/https://www.bisinfotech.com/new-door-in-the-beyond-cmos-world/ |archive-date=2022-05-13}}
* Nikonov, Dmitri E.; [[Ian A. Young|Ian A]]. (2013–12). "Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking". ''Proceedings of the IEEE''. '''101''' (12): 2498–2533. [[Doi (identifier)|doi]]:10.1109/jproc.2013.2252317. [[ISSN (identifier)|ISSN]] 0018-9219.
* Seabaugh, A.C. and Zhang, Q., 2010. Low-voltage tunnel transistors for beyond CMOS logic. ''Proceedings of the IEEE'', ''98''(12), pp. 2095–2110.
* Bernstein, K., Cavin, R.K., Porod, W., Seabaugh, A. and Welser, J., 2010. Device and architecture outlook for beyond CMOS switches. ''Proceedings of the IEEE'', ''98''(12), pp. 2169–2184.
* [[Sasikanth Manipatruni]], Nikonov, D.E. and [[Ian A. Young]], 2018. Beyond CMOS computing with spin and polarization. ''Nature Physics'', ''14''(4), pp. 338–343.
* Banerjee, S.K., Register, L.F., Tutuc, E., Basu, D., Kim, S., Reddy, D. and MacDonald, A.H., 2010. Graphene for CMOS and beyond CMOS applications. ''Proceedings of the IEEE'', ''98''(12), pp. 2032–2046.
* Topaloglu, R.O. and Wong, H.S.P. eds., 2019. ''Beyond-CMOS technologies for next generation computer design''. Berlin/Heidelberg, Germany: Springer.
* [[Sasikanth Manipatruni]], Nikonov, D.E., Lin, C.C., Gosavi, T.A., Liu, H., Prasad, B., Huang, Y.L., Bonturim, E., Ramesh, R. and Young, I.A., 2019. Scalable energy-efficient magnetoelectric spin–orbit logic. ''Nature'', ''565''(7737), pp. 35–42.

==External links==
* [https://web.archive.org/web/20151212172641/http://www.itrs.net/ITRS%201999-2014%20Mtgs%2C%20Presentations%20%26%20Links/2013ITRS/Summary2013.htm ITRS 2013 edition]
** [https://web.archive.org/web/20150920032846/http://www.itrs.net/ITRS%201999-2014%20Mtgs%2C%20Presentations%20%26%20Links/2013ITRS/2013Chapters/2013ERD_Summary.pdf EMERGING RESEARCH DEVICES SUMMARY]
** [https://web.archive.org/web/20150920035944/http://www.itrs.net/ITRS%201999-2014%20Mtgs%2C%20Presentations%20%26%20Links/2013ITRS/2013Chapters/2013PIDS_Summary.pdf Process Integration, Devices and structures summary]

[[Category:Electronic design]]
[[Category:Digital electronics]]
[[Category:Logic families]]
[[Category:Integrated circuits]]

Beyond CMOS - Revision history

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