View source for Bit manipulation instructions

{{Short description|Type of computer instructions}}
{{About|the general topic of Instruction set bit manipulation subsets|bit manipulation extensions unique to AMD and Intel|x86 Bit manipulation instruction set}}
{{Further|topic=bit manipulation in general, see|bit manipulation}}
{{primary sources|date=August 2025}}
{{Machine code}}
'''Bit manipulation instructions''' are [[instruction set architecture|instructions]] that perform [[bit manipulation]] operations in hardware, rather than requiring several instructions for those operations as illustrated with [[Bit manipulation#Example of bit manipulation|examples in software]].<ref>{{cite web | title=Bit Twiddling Hacks | url=https://graphics.stanford.edu/~seander/bithacks.html}}</ref> Several leading as well as historic architectures have bit manipulation instructions including [[ARM architecture family|ARM]], [[WDC 65C02]], the [[TX-2]] and the [[Power ISA]].<ref>{{cite web | title=Advanced bit manipulation instructions: Architecture, implementation and applications | website=[[ProQuest]] | url=https://www.proquest.com/openview/0ad3a2474b0691b65b35582fbdb3cf40/1?pq-origsite=gscholar&cbl=18750 }}</ref>

Bit manipulation is usually divided into subsets as individual instructions can be costly to implement in hardware when the target application has no justification. Conversely, if there ''is'' a justification then performance may suffer if the instruction is excluded. Carrying out the cost-benefit analysis is a complex task: one of the most comprehensive efforts in bit manipulation was a collaboration headed by Clare Wolfe, providing justifications, use-cases, c code, proofs and Verilog for each proposed RISC-V instruction.<ref>{{cite web | title=GitHub - riscv/Riscv-bitmanip at v0.93 | website=[[GitHub]] | url=https://github.com/riscv/riscv-bitmanip/tree/v0.93 }}</ref><ref>{{cite web |url=https://raw.githubusercontent.com/riscv/riscv-bitmanip/master/bitmanip-draft.pdf |title=RISC-V Bitmanip Extension Document Version 0.94-draft |editor=Claire Wolf |date=20 January 2021}}</ref>

Particular practical examples include [[bit banging]] of [[GPIO]] using a low-cost [[embedded controller]] such as the [[WDC 65C02]], [[8051]] and [[PIC instruction listings#Baseline core devices (12-bit)|Atmel PIC]]. At the slow clock rate of these CPUs, if bit-set/clear/test bit manipulation were not available these low-cost CPUs would not be fast enough to be for the target application.

<!-- {{WTMM-note|
In something of a Wikipedia [[Fourth wall]] breakage note: [[GPUs]] and other highly-specialist tasks such as cryptography tend to result in extreme-specialist instructions, wthout which performance would suck. Examples include [[AES instruction set]] extensions that cannot in any way be used for any other purpose. GPUs such as Larrabee<ref>{{cite web | title=TomF's talks and papers | url=https://tomforsyth1000.github.io/papers/papers.html }}</ref> and [[Single instruction, multiple threads#Nyuzi GPGPU|Nyuzi]] attempted to "dial back" this practice to some extent, only to discover why it is done (performance sucks otherwise... seeing a trend, here?).

This page is ''not'' about such specialised instructions, nor even of their functionality. It covers useful ''Categorisation'' of the ''existence'' in CPUs and CPU families, of ''general-purpose'' bit-manipulation instructions that ''happen'' to greatly improve performance or power consumption of specific algorithms. An example is cryptography making heavy use of [[Bitwise operation#Rotate|rotate]], but rotate having many other practical uses elsewhere: just not as many as, say, Add, which results in rotate being optional where Add does not. Such ISA design trade-offs are notoriously meticulous but ultimately pragmatic.

If you encounter any type of ''unusual or important'' bit manipulation instructions, or any CPU that has them, feel free to add them below, bearing in mind that the page's primary purpose is Categorisation, not explicit functional description per se. A helpful task for future readers would be to add such pages describing the functionality to the "See also" section. Enjoy the end of the Fourth Wall...
}}-->

== Hardware bit manipulation ==
{{Further|topic=categorisation of all types of bit and bitwise manipulation|Bit manipulation#Bit manipulation operations}}
{{Further|topic=a more complete list of find-first style instructions|Find first set#Hardware support}}
All the architectures below have instruction subsets and groups where the bit manipulation is provided in hardware. From the list it can be seen that [[digital signal processor|DSP]]s and [[embedded system|embedded]] [[microcontroller]]s have at least test/set/clear bit, however there are much more comprehensive instructions such as [[Count leading zeros]], [[Popcount]], [[Galois field]] arithmetic, [[binary-coded decimal]], bit-matrix multiply and transpose, byte-permute, bit permute including [[bit-reversal permutation|bit-reversal]], specialised cryptographic instructions and many more.

=== Intel and AMD (x86) ===
* The x86 instruction core set contains:
** {{code|BSR}} Bit Scan Reverse - Returns bit index of highest set bit in input, effectively backwards count leading zeros, not defined for 0.
** {{code|BSF}} Bit Scan Forward - Returns bit index of lowest set bit in input, effectively count trailing zeros, but not defined for 0.
* [[SSE4]] and the [[X86 Bit manipulation instruction set|BMI]] instruction set extensions contains instructions for:
** Count leading zeros - {{code|lzcnt}}
** Count trailing zeros - {{code|tzcnt}}
** Population count - {{code|popcnt}}
** Bit extract/bit deposit - {{code|pext}}/{{code|pdep}}
** Bit test - {{code|ptest}} and {{code|vptest}}, given two inputs, do both an {{code|AND}} operation and an {{code|ANDN}} operation between them, and set the ZF and CF EFLAGS bits on whether the results of the AND and ANDN, respectively, are 0. This can be used to test if all masked bits are zero, all masked bits are set, or a mix.
* The [[AVX-512#Bitwise ternary logic|AVX-512 ternary]] extension includes a [[bitwise ternary logic instruction]], {{code|vpternlog}}. Also noteworthy is a conflict detection instruction, [[AVX-512#Conflict detection|<code>VPCONFLICTD</code>]]
* Also present in the AVX/[[AVX-512]] [[GFNI instruction set|GFNI subset]] is bit-matrix affine transformation and its inverse: {{code|GF2P8AFFINEQB}} is effectively an 8x8 bit-matrix multiply in the [[Galois field]] GF(2^8).<ref>{{cite web | title=GF2P8AFFINEQB — Galois Field Affine Transformation | url=https://www.felixcloutier.com/x86/gf2p8affineqb }}</ref>
* AVX-512 BITALG besides AVX-512 version of existing bit manipulation instruction, also added {{code|VPSHUFBITQMB}} which is a bit-level shuffle instruction, that picks bits from one source using indexes in the second source.
* An Intel GNFI technology guide on that AVX/AVX512 GNFI Extension also lists numerous uses including parallel byte-wise set/clear/invert bitmanipulation, 5-bit sign-extension and points out the potential is much greater.<ref name=gfni>{{cite web |title=Galois Field New Instructions (GFNI) Technology Guide |url=https://networkbuilders.intel.com/solutionslibrary/galois-field-new-instructions-gfni-technology-guide |website=networkbuilders.intel.com |language=en}}</ref>
* [[Intel BCD opcodes]]

=== Power ISA ===
[[Power ISA]] has a large range of bit manipulation instructions,{{sfn|power3.1|loc=IBM Power ISA v3.1}} largely due to its history and relationship with IBM mainframes and the [[z/Architecture]]:
* [[Count leading zeros]] and trailing, and masked versions of the same.{{sfn|power3.1|loc=Power ISA Book I Chapter 3.3.13 Fixed-Point|p=104}} There is a mixture of [[popcount]]{{sfn|power3.1|loc=Power ISA Book I Chapter 3.3.13 Fixed-Point|p=104}} [[Parity bit|parity]]{{sfn|power3.1|loc=Power ISA Book I Chapter 3.3.13 Fixed-Point|p=103}} and [[SIMD within a register|SWAR]]-style instructions, but not a full set of each: {{code|popcntb}} is SWAR byte-level 8x8-bit but there is no 4x16-bit {{code|popcnth}} yet there is 2x32-bit {{code|popcntw}} and 64-bit scalar {{code|popcntd}}. Likewise, {{code|prtyw}} is SWAR half-word 4x16-bit but there is no {{code|prtyb}}
* masked bit-extract {{code|pextd}} and bit-deposit {{code|pdepd}} these drop and distribute bits in place according to a mask instead of the more usual technique of a offset and a length.;{{sfn|power3.1|loc=Power ISA Book I Chapter 3.3.13 Fixed-Point|p=106}} An unusual centrifuge instruction which moves masked-bits to the left and unmasked bits to the right, preserving their relative order in both instances. Most ISAs would have an operand expressing the number of sequential bits to extract, plus the length: {{code|cfuged}} combines these into one general-purpose bitmask.{{sfn|power3.1|loc=Power ISA Book I Chapter 3.3.13 Fixed-Point|p=106}} 
* 8x8-bit transpose {{code|vgbbd}}{{sfn|power3.1|loc=Power ISA Book I Chapter 6.12.1 Vector Facility|p=445}} which treats a 64-bit quantity as an 8x8 2D matrix, and performs a matrix transpose operation. Each bit 0 of each byte therefore becomes the first byte, each bit 1 of each byte becomes the second and so on.
* a strange but very useful indexing instruction, ({{code|bpermd}}){{sfn|power3.1|loc=Power ISA Book I Chapter 3.3.13 Fixed-Point|p=105}} which allows selection of up to eight individual bits from a 64-bit source, by treating each byte of a second 64-bit register as bit-indices into the first.
* Ternary 8-bit [[bitwise ternary logic instruction]] {{code|xxeval}}{{sfn|power3.1|loc=Power ISA Book I Chapter 7. Vector-Scalar Extension Facility|p=967}} similar to [[AVX-512]]
* strategic instructions for accelerating [[Binary-coded decimal#Packed BCD|packed BCD]]{{sfn|power3.1|loc=Power ISA Book I Chapter 3.3.15 Fixed-Point|p=117}} 
* Power v3.1 also introduced a number of additional bit manipulation instructions including swapping the order of bytes within half-words, words, and the whole 64-bit register.

=== Cray supercomputers ===
Cray patented BMM (Bit matrix multiply) in 1990 which could cope with up to 64x64-bit operands.<ref>{{cite web | title=Vector bit-matrix multiply functional unit | url=https://patents.google.com/patent/US5170370A/en }}</ref> The closest equivalent today is the 8x8 GF(2) Affine Transform instruction of AVX512.

=== IBM System/360 through z/Architecture ===

==== IBM System/360 ====
The [[IBM System/360]] has RR, RX and SI instructions for bit-wise and, exclusive or and or, RS arithmetic and logical shift{{efn|There are no rotate instructions in [[S/360]], [[S/370]] or [[ESA/370]].}} instructions, an SI test under mask{{efn|The immediate mask is 8 bits.}} and an atomic RX test and set instruction. These instructions and their extensions remain available through z/Architecture.

==== IBM System/370 ====
Toward the end of the [[S/370]] life cycle, IBM made move characters inverse, previously an RPQ, a standard instruction.

==== IBM S/370, S/370-XA, ESA/370, and ESA/390 vector operations ====
The [[IBM 3090]] introduced an optional [[vector processor|vector facility]]{{sfn|ibm370|loc=IBM System/370 Vector Operations|}} to the [[IBM System/370-XA|System/370-XA]] and [[Enterprise Systems Architecture/370]] instruction sets. In addition to integer and floating-point vector arithmetic and logical operations on multiple integer and floating-point values, it introduced vector bit manipulation operations [[count leading zeros]] {{code|vczvm}} and [[Hamming weight|population count]] {{code|vcovm}}.{{sfn|ibm370|pages=3{{hyp}}7-3{{hyp}}8|}}

==== ESA/390 ====
Towards the end of the [[ESA/390]] life cycle, IBM introduced some z/Architecture instructions in ESA/390. These included the rotate left single logical, load reversed and store reversed instructions.

==== z/Architecture scalar ====
[[z/Architecture]] inherited all of the bit manipulation instructions of its predecessors, and added 64-bit (''grande'') and long (20-bit) displacement versions of some.

<!-- Adjust case, sfn individual instructions -->
* General-instructions-extension facility{{sfn|z15|page=1{{hyp}}16}} adds
** ROTATE THEN AND SELECTED BITS{{sfn|z15|page=7{{hyp}}426}}
** ROTATE THEN EXCLUSIVE OR SELECTED BITS{{sfn|z15|page=7{{hyp}}427}}
** ROTATE THEN INSERT SELECTED BITS{{sfn|z15|page=7{{hyp}}427}}
** ROTATE THEN OR SELECTED BITS{{sfn|z15|page=7{{hyp}}427}}
* high-word facility{{sfn|z15|page=1{{hyp}}17}} adds
** ROTATE THEN INSERT SELECTED BITS HIGH{{sfn|z15|pages=7{{hyp}}430{{snd}}7{{hyp}}431}}
** ROTATE THEN INSERT SELECTED BITS Low{{sfn|z15|pages=7{{hyp}}430{{snd}}7{{hyp}}431}}
* Interlocked-Access Facility 1{{sfn|z15|page=1{{hyp}}18}} adds
** LOAD AND AND (LAN, LANG){{sfn|z15|pages=7{{hyp}}306{{snd}}7{{hyp}}307}}
** LOAD AND EXCLUSIVE OR (LAX, LAXG){{sfn|z15|page=7{{hyp}}307}} 
** LOAD AND OR (LAO, LAOG) (LAX, LAXG){{sfn|z15|pages=7{{hyp}}307{{snd}}7{{hyp}}308}}
* Miscellaneous-Instruction-Extensions Facility 1{{sfn|z15|page=1{{hyp}}25}} adds
** ROTATE THEN INSERT SELECTED BITS (RISBGN){{sfn|z15|pages=7{{hyp}}428{{snd}}7{{hyp}}430}}
* Miscellaneous-instruction-extensions facility 3 adds
** AND WITH COMPLEMENT (NCRK, NCGRK)
** MOVE RIGHT TO LEFT
** NAND (NNRK, NNGRK)
** NOT EXCLUSIVE OR (NXRK, NXGRK)
** NOR (NORK, NOGRK)
** OR WITH COMPLEMENT (OCRK, OCGRK)
** SELECT (SELR, SELGR)
** SELECT HIGH (SELFHR)
* Miscellaneous-Instruction-Extensions Facility 4{{sfn|z15|page=1{{hyp}}26}} adds
** BIT DEPOSIT (BDEPG){{sfn|z15|pages=7{{hyp}}35{{snd}}7{{hyp}}36}}
** BIT EXTRACT (BEXTG){{sfn|z15|page=7{{hyp}}36}}
** COUNT LEADING ZEROS (CLZG)
** COUNT TRAILING ZEROS (CTZG)

==== z/Architecture vector operations ====
<!-- Move scalar to previous section -->
<!-- Add other instructions -->
z/Architecture does not support the previous vector facility.{{sfn|z1|page=1{{hyp}}1}} However, starting with the 11th edition of the z/Architecture Principles of Operation:{{sfn|z11|page=xxviii}} it supports the following instructions:
* Vector [[count leading zeros]] {{code|vclz}}, [[count trailing zeros]] {{code|vctz}}{{sfn|z15|pages=22{{hyp}}11–22{{hyp}}12}}{{sfn|z15|pages=7{{hyp}}289-7{{hyp}}290}} and vector [[Hamming weight|population count]] {{code|vpopct}}{{sfn|z15|pages=22{{hyp}}26,7{{hyp}}424}}
* Vector test under mask {{code|vtm}}{{sfn|z15|page=22{{hyp}}37}} - sets a Condition Code based on comparing ''all'' elements of one register against a second vector as a mask: if all masked-comparisons are all-zero, if all are all-ones or a mix of both.
* Vector [[GF(2)]] multiply and multiply-accumulate, {{code|vgfm}},{{sfn|z15|page=22{{hyp}}16}} known as [[Finite field arithmetic#Carryless multiply|carryless multiply]]
* comprehensive  [[Binary-coded decimal#Packed BCD|packed BCD]].{{sfn|z15|pages=8{{hyp}}1-8{{hyp}}14}}
* memory-based test-and-set and various masked-test set/clear bit operations, which move or copy a single bit into Condition Codes.{{sfn|z15|pages=7{{hyp}}458-7{{hyp}}459}}

=== DEC PDP-10 ===
The DEC [[PDP-6]] and [[PDP-10]] had logical operations covering the full suite of 2-operand [[lookup table#Hardware LUTs|hardware lookup table]] (LUT2) [[Boolean function]]s{{sfn|pdp10|p=2{{hyp}}38|at=2.4 Boolean Functions|}} (rather than the 3-operand functions that AVX512 and Power ISA have).

Later models of the PDP-10 had instructions to convert between [[Binary-coded decimal#Packed BCD|packed BCD]] and binary.{{sfn|pdp10|pages=2{{hyp}}99|}}

Also present is unusual (variable-bit-length) byte load and store instructions that use ''byte pointers'' for memory operands: in modern terminology these are bit-field insert and extract. In addition to a word address, the bit length (S) and the bit offset (P) of the byte from which to load or into which to store are specified. These instructions can specify a byte size of 0-36, but a byte may not straddle a word boundary.{{sfn|pdp10|pages=2{{hyp}}85-2{{hyp}}89|loc=Byte manipulation|}} The string manipulation,{{sfn|pdp10|pages=2{{hyp}}91-2{{hyp}}99|loc=2.12 String Manipulation|}} BCD/binary conversion,{{sfn|pdp10|pages=2{{hyp}}98-2{{hyp}}103|loc=2.13 Decimal Conversion|}} and string editing{{sfn|pdp10|pages=2{{hyp}}104-2{{hyp}}112|loc=2.14 String Editing|}} instructions in later models use byte pointers and have the same restrictions.

===GE-600 series===

The [[GE-600 series]] and its successors had Gray-to-binary conversion; without such an instruction, [[Gray code#Converting to and from Gray code|converting from Gray code]] requires multiple steps. Binary-to-Gray is simply {{code|x^(x>>1)}} and does not justify a dedicated instruction. Gray coding has significant [[Gray code#History and practical application|practical applications]].

=== ARM ===
* [[ARM11]] has bitwise test-ANDed (a bitmasked test) and test-XOR, standard logical [[bitwise operations]] including OR-complement; byte halfword and bit-reversing, and conditional byte-selection/merging. Shift and rotate are available on Operand2.<ref>{{cite web |url=https://pages.cs.wisc.edu/~markhill/restricted/arm_isa_quick_reference.pdf |title=ARM Instruction Set Quick Reference Card |date=October 2003}}</ref>
* ARM Cortex-A has bit-field set, clear, extract and reverse.<ref>{{cite web | title=Documentation – Arm Developer | url=https://developer.arm.com/documentation/den0013/d/ARM-Thumb-Unified-Assembly-Language-Instructions/Miscellaneous-instructions/Bit-manipulation }}</ref>
* ARM A64 has [[SIMD within a register|SWAR]]-style half-word byte-swapping, bit-field insert and extract, and bit-reversing.<ref>{{cite web | title=Documentation – Arm Developer | url=https://developer.arm.com/documentation/102374/0102/Data-processing---bit-manipulation }}</ref>

=== RISC-V ===
In the standard extensions RISC-V has scalar [[bitwise operations]] including shift and arithmetic shift, but no rotate. The omissions are compensated for with additional extensions.
* [[RISC-V]] Zb* extensions contain a significant number of bit manipulation instructions.<ref>{{cite web | title=Riscv-bitmanip/Bitmanip/Index.adoc at main · riscv/Riscv-bitmanip | website=[[GitHub]] | url=https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/index.adoc }}</ref> The four groups are broken down into useful categories (the integer subset has min/max, rotate and [[popcount]] for example), and have very  well-researched justifications for their inclusion and the improvements they bring.<ref>{{cite web | title=Riscv-bitmanip/Bitmanip/Overview.adoc at main · riscv/Riscv-bitmanip | website=[[GitHub]] | url=https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/overview.adoc }}</ref>
* The RISC-V Vector Extension (RVV) has instructions that qualify as hardware-level bit manipulation, but on Vector masks rather than Scalar registers as is normally the case. For example, a Vector-mask [[Popcount]] is available.<ref>{{cite web | title=Riscv-v-spec/V-spec.adoc at master · riscvarchive/Riscv-v-spec | website=[[GitHub]] | url=https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#15-vector-mask-instructions }}</ref> RVV also has per-element [[bitwise operations]].<ref>{{cite web | title=Riscv-v-spec/V-spec.adoc at master · riscvarchive/Riscv-v-spec | website=[[GitHub]] | url=https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#115-vector-bitwise-logical-instructions }}</ref>

=== Embedded microcontrollers ===

==== Intel ====
* The [[8086]] has {{code|TEST}}, as well as [[bitwise operations]]<ref>{{cite web | title=Bit Manipulation Instructions in 8086 &#124; Logical Instructions | date=11 August 2018 | url=https://www.eeeguide.com/bit-manipulation-instructions-in-8086/ }}</ref>
* The [[8051]] has {{code|SETB}}, {{code|CLR}} and {{code|CPL}} - set clear and invert bit instructions - and a considerable percentage of its instructions are bit manipulation.<ref>{{cite web |url=https://cs.uok.edu.in/Files/79755f07-9550-4aeb-bd6f-5d802d56b46d/Custom/InstructionSet_UnitII.pdf |title=8051 Instructions}}</ref> Also included is Or-complement and And-complement, present in RISC-V Zb*.<ref>{{cite web | title=Boolean (Bitwise) instructions in 8051 for bit manipulation | date=29 April 2020 | url=https://technobyte.org/bit-operations-8051-boolean-instructions/ }}</ref>

==== Zilog Z80 ====
* The [[Zilog Z80]] [[Z80 instruction set|instruction set]] includes {{code|BIT}}, {{code|RES}}, and {{code|SET}} instructions. These test, reset, and set individual bits in registers or memory pointed to by HL, IX, or IY.<ref>{{Cite book |url=https://www.zilog.com/docs/z80/um0080.pdf#G5.1130345 |title=Z80 Family CPU User Manual |publisher=[[Zilog]] |year=2016 |id=UM008011-0816 |access-date=January 5, 2024 |archive-url=https://web.archive.org/web/20231226131929/http://www.zilog.com/docs/z80/um0080.pdf#G5.1130345 |archive-date=December 26, 2023 |url-status=live}}</ref>

==== MOS 6502 ====
{{see also|MOS Technology 6502#Variations and derivatives}}
* The [[WDC 65C02]] added [[WDC 65C02#Bit manipulation instructions|bit-manipulation]]:test and set (TSB) and test and reset (TRB) on individual bits.
* Rockwell added similar extensions (RMB, SMB, BBR and BBS) to the R65C00 series<ref>{{cite web
|title=Rockwell R6500/11, R6500/12 and R6500/15 One-Chip Microcomputers
|url=https://datasheetspdf.com/pdf-file/1338410/Rockwell/R6500-11/1
|date=7 June 1987
|access-date=30 April 2020
|archive-date=3 September 2023
|archive-url=https://web.archive.org/web/20230903114502/https://datasheetspdf.com/pdf-file/1338410/Rockwell/R6500-11/1
|url-status=dead
}}</ref>

==== Microchip PICs ====
* The [[Microchip Technology]] [[PIC microcontrollers|PIC range]] also has [[bitwise operations]] and set, clear and test bit, listed in the [[PIC instruction listings#Baseline core devices (12-bit)|instructions]].

=== Others ===
* [[Texas Instruments]] [[Digital signal processor|DSP]]s such as the [[TMS320#C6000 series|TMS320C6000]] series have set, clear, invert, test, extract and insert bit (or bit-field) instructions.<ref>{{cite web |url=https://www.ti.com/lit/ug/spru198k/spru198k.pdf |title=TMS320C6000 Programmer’s Guide |publisher=[[Texas Instruments]] |date=July 2011}}</ref>
* The [[TX-2]] from 1958 had [[Predication (computer architecture)|"skip on bit" predication]], as well as set, clear, invert and permute bits, and shift and other [[bitwise operations]].<ref>{{cite web | title=TX-2 Documentation | url=https://tx-2.github.io/documentation.html }}</ref><ref>{{cite book |chapter-url=http://www.bitsavers.org/pdf/mit/tx-2/TX-2_UserHandbook_ch3.pdf |chapter=Chapter 3 - Operation Code |title=TX-2 User's Handbook}}</ref>
* [[SuperH]] has comprehensive memory-based bit manipulation including And-complement and Or-complement, but also has standard register-based test/set/clear and an unusual instruction that replaces bit N (in the range 0 to 7) and copies the replaced bit into the Test register.<ref>{{cite web | title=Renesas SH Instruction Set Summary | url=https://shared-ptr.com/sh_insns.html }}</ref>
* The [[Signetics]] [[Signetics 8X300|8X300]] is a microprocessor introduced in 1976. The processor normally manipulates 8-bit data bytes, but the mask and rotate units makes it possible to manipulate single or multiple bits, making this a variable data-length processor.
* The [[Digital Equipment Corporation|DEC]] [[PDP-11 architecture]] from 1970 supports bit testing, setting, and clearing on both words <code>BIT</code><code>BIS</code><code>BIC</code> and bytes <code>BITB</code><code>BISB</code><code>BICB</code>. The very similar [[WD16]] supports only the word forms of these instructions plus <code>BISB</code>. The WD16 additionally supports faster byte-addressed flags with its <code>TSTB</code><code>SETB</code><code>CLRB</code> and <code>COMB</code> (compliment) instructions. The PDP-11 is missing the <code>SETB</code> instruction.
* The [[Motorola 68000]] supports bit test and manipulation of memory or data registers. The bit number may either be an immediate or a value in a data register. The instructions are: <code>BSET</code> (set to 1), <code>BCLR</code> (clear to 0), <code>BCHG</code> (invert) and <code>BTST</code> (no change). All of these instructions first test the destination bit and set the CCR Z bit if the destination bit is 0.

== Notes ==
{{notelist}}

== See also ==
{{columns-list|colwidth=26em|
* {{Annotated link|Find first set}}
* {{Annotated link|Bitwise operation}}
* {{Annotated link|Popcount}}
* {{Annotated link|Count leading zeros}}
* {{Annotated link|Mask (computing)}}
* {{Annotated link|Binary-coded decimal}}
* {{Annotated link|CLMUL instruction set}}
* {{Annotated link|Bitwise ternary logic instruction}}
* {{Annotated link|GFNI instruction set}}
}}

== References ==
:{{cite book
 | title       = z/Architecture Principles of Operation
 | id          = SA22-7832-00
 | date        = December 2000
 | edition     = First
 | ref         = {{sfnref|z1}}
 | url         = https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr000.pdf
 | publisher   = [[IBM]]
 | access-date = August 8, 2025
 }}
:{{cite book
 | title       = z/Architecture Principles of Operation
 | id          = SA22-7832-10
 | date        = March 2015
 | edition     = Eleventh
 | ref         = {{sfnref|z11}}
 | url         = https://publibfp.dhe.ibm.com/epubs/pdf/dz9zr010.pdf
 | publisher   = [[IBM]]
 | access-date = August 8, 2025
 }}
:{{cite book
 | title       = z/Architecture Principles of Operation
 | id          = SA22-7832-14
 | date        = April 2025
 | edition     = Fifteenth
 | ref         = {{sfnref|z15}}
 | url         = https://www.ibm.com/docs/en/module_1678991624569/pdf/SA22-7832-14.pdf
 | publisher   = [[IBM]]
 | access-date = July 3, 2025
 }}
<!-- Check https://linux.mainframe.blog/zarchitecture-principles-of-operation/ for newer editions -->
:{{cite book
 | title       = Power ISA™ Version 3.1
 | id          = SA22-7832-14
 | date        = May 1, 2020
 | edition     = v3.1
 | ref         = {{sfnref|power3.1}}
 | url         = https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf
 | publisher   = [[IBM]]
 | access-date = Aug 7, 2025
 }}
:{{cite book
 |       title = IBM System/370 Vector Operations
 |          id = SA22-7125-2
 |        date = August 1986
 |     edition = Third
 | ref         = {{sfnref|ibm370}}
 |         url = http://bitsavers.org/pdf/ibm/370/vectorFacility/SA22-7125-2_Vector_Operations_Aug87.pdf
 | access-date = Sep 20, 2018
 |   publisher = IBM Corporation
 }}
:{{Cite book
 | title       = DECsystem-10 - DECSYSTEM--20 - Processor Reference Manual 
 | id          = AA-H391A-TK, AD-4391A-T1
 | ref         = {{sfnref|pdp10}}
 | url         = http://www.bitsavers.org/pdf/dec/pdp10/1982_ProcRefMan.pdf
 | access-date = August 8, 2025
 | publisher   = [[Digital Equipment Corporation]]
 | via         = bitsavers.org
 }}
{{Reflist}}

== Further reading ==
* {{cite thesis |last1=Hilewitz |first1=Yedidya |title=Advanced bit manipulation instructions: Architecture, implementation and applications |date=2008 |publisher=[[Princeton University]] |degree=PhD |url=https://www.proquest.com/openview/0ad3a2474b0691b65b35582fbdb3cf40/1.pdf?pq-origsite=gscholar&cbl=18750}}
** {{cite book |last1=Hilewitz |first1=Yedidya |last2=Lee |first2=Ruby B. |title=Advanced Bit Manipulation Instruction Set Architecture. Technical Report CE-L2006-004 |date=November 2006 |publisher=Princeton University Department of Electrical Engineering |url=https://www.researchgate.net/publication/249884287}}
* {{cite conference |last1=Koppelmann |first1=Bastian |last2=Adelt |first2=Peer |last3=Mueller |first3=Wolfgang |last4=Scheytt |first4=Christoph |conference=2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) |title=RISC-V Extensions for Bit Manipulation Instructions |publisher=IEEE |date=2019 |pages=41–48 |isbn=978-1-7281-2103-1 |doi=10.1109/PATMOS.2019.8862170 }}

{{Instruction set extensions}}

[[Category:Instruction set extensions]]