Editing Serial Peripheral Interface (section)

== Bus topologies ==
Though the previous operation section focused on a basic interface with a single slave, SPI can instead communicate with multiple slaves using multidrop, daisy chain, or expander configurations.

===Multidrop configuration===
[[File:SPI_three_slaves.svg|thumb|216x216px|Multidrop SPI bus]]
In the [[multidrop bus]] configuration, each slave has its own {{Overline|SS}}, and the master selects only one at a time. MISO, SCLK, and MOSI are each shared by all devices. This is the way SPI is normally used.

Since the MISO pins of the slaves are connected together, they are required to be tri-state pins (high, low or high-impedance), where the high-impedance output must be applied when the slave is not selected. Slave devices not supporting tri-state may be used in multidrop configuration by adding a tri-state buffer chip controlled by its {{Overline|SS}} signal.<ref name="Better SPI Bus Design in 3 Steps">[https://www.pjrc.com/better-spi-bus-design-in-3-steps/ Better SPI Bus Design in 3 Steps]</ref> (Since only a single signal line needs to be tristated per slave, one typical standard logic chip that contains four tristate buffers with independent gate inputs can be used to interface up to four slave devices to an SPI bus)<blockquote>Caveat: All {{Overline|SS}} signals should start high (to indicate no slaves are selected) before sending initialization messages to any slave, so other uninitialized slaves ignore messages not addressed to them. This is a concern if the master uses [[General-purpose input/output|general-purpose input/output (GPIO) pins]] (which may default to an undefined state) for {{Overline|SS}} and if the master uses separate software libraries to initialize each device. One solution is to configure all GPIOs used for {{Overline|SS}} to output a high voltage for ''all'' slaves ''before'' running initialization code from any of those software libraries. Another solution is to add a [[pull-up resistor]] on each {{Overline|SS}}, to ensure that all {{Overline|SS}} signals are initially high.<ref name="Better SPI Bus Design in 3 Steps" /></blockquote>

===Daisy chain configuration===
[[File:SPI_three_slaves_daisy_chained.svg|thumb|229x229px|Daisy-chained SPI]]
Some products that implement SPI may be connected in a [[Daisy chain (electrical engineering)|daisy chain]] configuration, where the first slave's output is connected to the second slave's input, and so on with subsequent slaves, until the final slave, whose output is connected back to the master's input. This effectively merges the individual communication shift registers of each slave to form a single larger combined [[shift register]] that shifts data through the chain. This configuration only requires a single {{Overline|SS}} line from the master, rather than a separate {{Overline|SS}} line for each slave.<ref>[https://www.maximintegrated.com/en/app-notes/index.mvp/id/3947 Maxim-IC application note 3947: "Daisy-Chaining SPI Devices"]</ref>

In addition to using SPI-specific slaves, daisy-chained SPI can include [[Discrete component|discrete]] shift registers for [[Shift register#More I/O pins|more pins]] of inputs (e.g. using the [[Shift register#Parallel-in serial-out (PISO)|parallel-in serial-out]] [[List of 7400-series integrated circuits|74]]<nowiki/>xx165)<ref name=":3">{{Cite web |last=Gammon |first=Nick |date=2013-03-23 |title=Gammon Forum : Electronics : Microprocessors : Using a 74HC165 input shift register |url=https://www.gammon.com.au/forum/?id=11979 |url-status=live |archive-url=https://web.archive.org/web/20230729042912/http://www.gammon.com.au/forum/?id=11979 |archive-date=2023-07-29 |access-date=2023-08-03 |website=Gammon Forum}}</ref> or outputs (e.g. using the [[Shift register#Serial-in parallel-out (SIPO)|serial-in parallel-out]] [[List of 7400-series integrated circuits|74]]<nowiki/>xx595)<ref name=":2">{{Cite web |last=Gammon |first=Nick |date=2012-01-31 |title=Gammon Forum : Electronics : Microprocessors : Using a 74HC595 output shift register as a port-expander |url=https://www.gammon.com.au/forum/?id=11518 |url-status=live |archive-url=https://web.archive.org/web/20230714101259/http://www.gammon.com.au/forum/?id=11518 |archive-date=2023-07-14 |access-date=2023-08-03 |website=Gammon Forum}}</ref> chained indefinitely. Other applications that can potentially interoperate with daisy-chained SPI include [[SGPIO]], [[JTAG]],<ref>{{citation |title= Interfaces |year = 1977|url= https://books.google.com/books?id=8od7phxJHGkC |pages= 80, 84}}</ref> and [[I2C|I<sup>2</sup>C]].

===Expander configurations===
Expander configurations use SPI-controlled addressing units (e.g. [[Binary decoder|binary decoders]], [[Demultiplexer|demultiplexers]], or shift registers) to add chip selects.

For example, one {{Overline|SS}} can be used for transmitting to a SPI-controlled demultiplexer an index number controlling its select signals, while another {{Overline|SS}} is routed through that demultiplexer according to that index to select the desired slave.<ref>{{cite web |date=2001-07-01 |title=Serial-Control Multiplexer Expands SPI Chip Selects |url=http://www.farnell.com/datasheets/312519.pdf |archive-url=https://web.archive.org/web/20190819062018/http://www.farnell.com/datasheets/312519.pdf |archive-date=2019-08-19 |access-date= |website=[[Premier Farnell]]}}</ref>