Editing Coherent Accelerator Processor Interface (section)

==== OMI ====
OpenCAPI Memory Interface (OMI) is a [[Serial communication#Serial versus parallel|serial attached]] [[Random-access memory|RAM]] technology based on OpenCAPI, providing [[Latency (engineering)|low latency]], [[Bandwidth (computing)|high bandwidth]] connection for main memory. OMI uses a controller chip on the memory modules that allows for technology agnostic approach to what is used on the modules, be it [[DDR4 SDRAM|DDR4]], [[DDR5 SDRAM|DDR5]], [[High Bandwidth Memory|HBM]] or storage class [[non-volatile random-access memory|non-volatile RAM]]. An OMI based CPU can therefore change RAM type by changing the memory modules.

A serial connection uses less floorspace for the interface on the CPU die therefore potentially allowing more of them compared to using common DDR memory.

OMI is implemented in IBM's [[Power10]] CPU, which has 8 OMI memory controllers on-chip, allowing for 4 TB RAM and 410 GB/s memory bandwidth per processor. These DDIMMs (Differential Dynamic Memory Module) includes an OMI controller and memory buffer, and can address individual memory chips for fault tolerance and redundancy purposes.

[[Microchip Technology]] manufactures the OMI controller on the DDIMMs. Their SMC 1000 OpenCAPI memory is described as "the next progression in the market adopting serial attached memory."<ref>{{citation
|author=Patrick Kennedy
|url=https://www.servethehome.com/microchip-smc-1000-for-the-serial-attached-memory-future/
|date=August 5, 2019
|title=Microchip SMC 1000 For The Serial Attached Memory Future
|publisher=Servethehome}}</ref>