Editing Bit manipulation instructions (section)

=== IBM System/360 through z/Architecture ===

==== IBM System/360 ====
The [[IBM System/360]] has RR, RX and SI instructions for bit-wise and, exclusive or and or, RS arithmetic and logical shift{{efn|There are no rotate instructions in [[S/360]], [[S/370]] or [[ESA/370]].}} instructions, an SI test under mask{{efn|The immediate mask is 8 bits.}} and an atomic RX test and set instruction. These instructions and their extensions remain available through z/Architecture.

==== IBM System/370 ====
Toward the end of the [[S/370]] life cycle, IBM made move characters inverse, previously an RPQ, a standard instruction.

==== IBM S/370, S/370-XA, ESA/370, and ESA/390 vector operations ====
The [[IBM 3090]] introduced an optional [[vector processor|vector facility]]{{sfn|ibm370|loc=IBM System/370 Vector Operations|}} to the [[IBM System/370-XA|System/370-XA]] and [[Enterprise Systems Architecture/370]] instruction sets. In addition to integer and floating-point vector arithmetic and logical operations on multiple integer and floating-point values, it introduced vector bit manipulation operations [[count leading zeros]] {{code|vczvm}} and [[Hamming weight|population count]] {{code|vcovm}}.{{sfn|ibm370|pages=3{{hyp}}7-3{{hyp}}8|}}

==== ESA/390 ====
Towards the end of the [[ESA/390]] life cycle, IBM introduced some z/Architecture instructions in ESA/390. These included the rotate left single logical, load reversed and store reversed instructions.

==== z/Architecture scalar ====
[[z/Architecture]] inherited all of the bit manipulation instructions of its predecessors, and added 64-bit (''grande'') and long (20-bit) displacement versions of some.

<!-- Adjust case, sfn individual instructions -->
* General-instructions-extension facility{{sfn|z15|page=1{{hyp}}16}} adds
** ROTATE THEN AND SELECTED BITS{{sfn|z15|page=7{{hyp}}426}}
** ROTATE THEN EXCLUSIVE OR SELECTED BITS{{sfn|z15|page=7{{hyp}}427}}
** ROTATE THEN INSERT SELECTED BITS{{sfn|z15|page=7{{hyp}}427}}
** ROTATE THEN OR SELECTED BITS{{sfn|z15|page=7{{hyp}}427}}
* high-word facility{{sfn|z15|page=1{{hyp}}17}} adds
** ROTATE THEN INSERT SELECTED BITS HIGH{{sfn|z15|pages=7{{hyp}}430{{snd}}7{{hyp}}431}}
** ROTATE THEN INSERT SELECTED BITS Low{{sfn|z15|pages=7{{hyp}}430{{snd}}7{{hyp}}431}}
* Interlocked-Access Facility 1{{sfn|z15|page=1{{hyp}}18}} adds
** LOAD AND AND (LAN, LANG){{sfn|z15|pages=7{{hyp}}306{{snd}}7{{hyp}}307}}
** LOAD AND EXCLUSIVE OR (LAX, LAXG){{sfn|z15|page=7{{hyp}}307}} 
** LOAD AND OR (LAO, LAOG) (LAX, LAXG){{sfn|z15|pages=7{{hyp}}307{{snd}}7{{hyp}}308}}
* Miscellaneous-Instruction-Extensions Facility 1{{sfn|z15|page=1{{hyp}}25}} adds
** ROTATE THEN INSERT SELECTED BITS (RISBGN){{sfn|z15|pages=7{{hyp}}428{{snd}}7{{hyp}}430}}
* Miscellaneous-instruction-extensions facility 3 adds
** AND WITH COMPLEMENT (NCRK, NCGRK)
** MOVE RIGHT TO LEFT
** NAND (NNRK, NNGRK)
** NOT EXCLUSIVE OR (NXRK, NXGRK)
** NOR (NORK, NOGRK)
** OR WITH COMPLEMENT (OCRK, OCGRK)
** SELECT (SELR, SELGR)
** SELECT HIGH (SELFHR)
* Miscellaneous-Instruction-Extensions Facility 4{{sfn|z15|page=1{{hyp}}26}} adds
** BIT DEPOSIT (BDEPG){{sfn|z15|pages=7{{hyp}}35{{snd}}7{{hyp}}36}}
** BIT EXTRACT (BEXTG){{sfn|z15|page=7{{hyp}}36}}
** COUNT LEADING ZEROS (CLZG)
** COUNT TRAILING ZEROS (CTZG)

==== z/Architecture vector operations ====
<!-- Move scalar to previous section -->
<!-- Add other instructions -->
z/Architecture does not support the previous vector facility.{{sfn|z1|page=1{{hyp}}1}} However, starting with the 11th edition of the z/Architecture Principles of Operation:{{sfn|z11|page=xxviii}} it supports the following instructions:
* Vector [[count leading zeros]] {{code|vclz}}, [[count trailing zeros]] {{code|vctz}}{{sfn|z15|pages=22{{hyp}}11–22{{hyp}}12}}{{sfn|z15|pages=7{{hyp}}289-7{{hyp}}290}} and vector [[Hamming weight|population count]] {{code|vpopct}}{{sfn|z15|pages=22{{hyp}}26,7{{hyp}}424}}
* Vector test under mask {{code|vtm}}{{sfn|z15|page=22{{hyp}}37}} - sets a Condition Code based on comparing ''all'' elements of one register against a second vector as a mask: if all masked-comparisons are all-zero, if all are all-ones or a mix of both.
* Vector [[GF(2)]] multiply and multiply-accumulate, {{code|vgfm}},{{sfn|z15|page=22{{hyp}}16}} known as [[Finite field arithmetic#Carryless multiply|carryless multiply]]
* comprehensive  [[Binary-coded decimal#Packed BCD|packed BCD]].{{sfn|z15|pages=8{{hyp}}1-8{{hyp}}14}}
* memory-based test-and-set and various masked-test set/clear bit operations, which move or copy a single bit into Condition Codes.{{sfn|z15|pages=7{{hyp}}458-7{{hyp}}459}}