Editing Universal asynchronous receiver-transmitter (section)

===Receiver===
All operations of the UART hardware are controlled by an internal clock signal, which runs at a multiple of the data rate, typically 8 or 16 times the bit rate. The receiver tests the state of the incoming signal on each clock pulse, looking for the beginning of the start bit. If the apparent start bit lasts at least one-half of the bit time, it is valid and signals the start of a new character. If not, it is considered a spurious pulse and is ignored. After waiting a further bit time, the state of the line is again sampled and the resulting level clocked into a shift register. After the required number of bit periods for the character length (5 to 8 bits, typically) have elapsed, the contents of the shift register are made available (in parallel fashion) to the receiving system. The UART will set a flag indicating new data is available, and may also generate a processor [[interrupt]] to request that the host processor transfer the received data.

Communicating UARTs have no shared timing system apart from the communication signal. Typically, UARTs resynchronize their internal clocks on each change of the data line that is not considered a spurious pulse. Obtaining timing information in this manner, they reliably receive when the transmitter is sending at a slightly different speed than it should. Simplistic UARTs do not do this; instead, they resynchronize on the falling edge of the start bit only, and then read the center of each expected data bit, and this system works if the broadcast data rate is accurate enough to allow the stop bits to be sampled reliably.<ref name="AN2141">{{cite web |title=Determining Clock Accuracy Requirements for UART Communications |url=https://pdfserv.maximintegrated.com/en/an/AN2141.pdf |website=an2141 |publisher=[[Maxim Integrated]] |access-date=1 November 2021 |language=EN |date=2003-08-07}}</ref><ref name="nxp_SCC2691">{{cite web |author1= |title=Universal asynchronous receiver/transmitter (UART) |url=https://www.nxp.com/docs/en/data-sheet/SCC2691.pdf#page=14 |website=SCC2691 |publisher=Philips [[NXP]] |access-date=1 November 2021 |page=14 |language=en |format=PDF |date=2006-08-04 }}</ref>

It is a standard feature for a UART to store the most recent character while receiving the next. This "double buffering" gives a receiving computer an entire character transmission time to fetch a received character. Many UARTs have a small first-in, first-out FIFO buffer memory between the receiver shift register and the host system interface. This allows the host processor even more time to handle an interrupt from the UART and prevents loss of received data at high rates.