Editing Coherent Accelerator Processor Interface (section)

==== CAPI ====
CAPI is layered on top of [[PCI Express#PCI Express 3.0|PCIe Gen 3]], using 16 PCIe lanes, and is an additional functionality for the PCIe slots on CAPI enabled systems. Usually there are designated CAPI enabled PCIe slots on such machines. Since there is only one CAPP per POWER8 processor the number of possible CAPI units are determined by the number of POWER8 processors, regardless of how many PCIe slots there are. In certain POWER8 systems, IBM makes use of dual chip modules, thus doubling the CAPI capacity per processor socket.

Traditional transactions between a PCIe device and a CPU can take around 20,000 operations, whereas a CAPI attached device will only use around 500, significantly reducing latency, and effectively increasing bandwidth due to decreased operations overhead.<ref name="RAWkeynote" />

The total bandwidth of a CAPI port is determined by the underlying PCIe 3.0 x16 technology, peaking at ca 16 GB/s, bidirectional.<ref name="nextplatform-capi">[http://www.nextplatform.com/2016/10/17/opening-server-bus-coherent-acceleration/ Opening Up The Server Bus For Coherent Acceleration]</ref>