Editing Advanced eXtensible Interface (section)

== AXI ==

=== Signals ===

{| class="wikitable"
|+ Signals of the Read and Write Address channels
|-
! Signal description !! Write Address channel !! Read Address channel
|-
| Address ID, to identify multiple [[Stream (computing)|streams]] over a single [[Communication channel|channel]] || AWID || ARID
|-
| Address of the first beat of the burst || AWADDR || ARADDR
|-
| Number of beats inside the burst || AWLEN{{refn|name=axi34difference|group=nb|Different behavior between AXI3 and AXI4}} || ARLEN{{refn|name=axi34difference|group=nb}}
|-
| Size of each beat || AWSIZE || ARSIZE
|-
| Type of the burst || AWBURST || ARBURST
|-
| Lock type, to provide [[Atomicity (programming)|atomic operations]] || AWLOCK{{refn|name=axi34difference|group=nb}} || ARLOCK{{refn|name=axi34difference|group=nb}}
|-
| Memory type, how the transaction has to progress through the system || AWCACHE || ARCACHE
|-
| Protection type: [[Privilege (computing)|privilege]], security level and data/instruction access || AWPROT || ARPROT
|-
| [[Quality of service]] of the transaction || AWQOS{{refn|name=axi4only|group=nb|Available only with AXI4}} || ARQOS{{refn|name=axi4only|group=nb}}
|-
| Region identifier, to access multiple logical interfaces from a single physical one || AWREGION{{refn|name=axi4only|group=nb}} || ARREGION{{refn|name=axi4only|group=nb}}
|-
| User-defined data || AWUSER{{refn|name=axi4only|group=nb}} || ARUSER{{refn|name=axi4only|group=nb}}
|-
| <code>xVALID</code> [[Handshake (computing)|handshake]] signal || AWVALID || ARVALID
|-
| <code>xREADY</code> [[Handshake (computing)|handshake]] signal || AWREADY || ARREADY
|}

{| class="wikitable"
|+ Signals of the Read and Write Data channels
|-
! Signal description !! Write Data channel !! Read Data channel
|-
| Data ID, to identify multiple [[Stream (computing)|streams]] over a single [[Communication channel|channel]] || WID{{refn|name=axi3only|group=nb|Available only with AXI3}} || RID
|-
| Read/Write data || WDATA || RDATA
|-
| Read response, to specify the status of the current RDATA signal || || RRESP 
|-
| Byte strobe, to indicate which bytes of the WDATA signal are valid || WSTRB || 
|-
| Last beat identifier || WLAST || RLAST
|-
| User-defined data || WUSER{{refn|name=axi4only|group=nb}} || RUSER{{refn|name=axi4only|group=nb}}
|-
| <code>xVALID</code> [[Handshake (computing)|handshake]] signal || WVALID || RVALID
|-
| <code>xREADY</code> [[Handshake (computing)|handshake]] signal || WREADY || RREADY
|}

{| class="wikitable"
|+ Signals of the Write Response channel
|-
! Signal description !! Write Response channel
|-
| Write response ID, to identify multiple [[Stream (computing)|streams]] over a single [[Communication channel|channel]] || BID
|-
| Write response, to specify the status of the burst || BRESP
|-
| User-defined data || BUSER{{refn|name=axi4only|group=nb}}
|-
| <code>xVALID</code> [[Handshake (computing)|handshake]] signal || BVALID
|-
| <code>xREADY</code> [[Handshake (computing)|handshake]] signal || BREADY
|}
<ref>{{cite web |author1=Arm Holdings |title=AMBA AXI and ACE Protocol Specification |url=https://static.docs.arm.com/ihi0022/e/IHI0022E_amba_axi_and_ace_protocol_spec.pdf |website=developer.arm.com |access-date=5 July 2019 |pages=28–34 |language=en |archive-date=5 July 2019 |archive-url=https://web.archive.org/web/20190705083043/https://static.docs.arm.com/ihi0022/e/IHI0022E_amba_axi_and_ace_protocol_spec.pdf |url-status=dead }}</ref>
{{reflist|group=nb}}

=== Bursts ===
[[File:AXI_Bursts.svg|thumb|upright=1.5|Example of FIXED, INCR and WRAP bursts]]

AXI is a [[Burst mode (computing)|burst-based]] [[Communication protocol|protocol]],<ref>{{cite web |author1=Arm Holdings |title=AMBA AXI and ACE Protocol Specification |url=https://static.docs.arm.com/ihi0022/e/IHI0022E_amba_axi_and_ace_protocol_spec.pdf |website=developer.arm.com |access-date=5 July 2019 |page=22 |language=en |archive-date=5 July 2019 |archive-url=https://web.archive.org/web/20190705083043/https://static.docs.arm.com/ihi0022/e/IHI0022E_amba_axi_and_ace_protocol_spec.pdf |url-status=dead }}</ref> meaning that there may be multiple data transfers (or beats) for a single request. This makes it useful in the cases where it is necessary to transfer large amount of data from or to a specific pattern of addresses.
In AXI, bursts can be of three types, selected by the signals ARBURST (for reads) or AWBURST (for writes):<ref>{{cite web |author1=Arm Holdings |title=AMBA AXI and ACE Protocol Specification |url=https://static.docs.arm.com/ihi0022/e/IHI0022E_amba_axi_and_ace_protocol_spec.pdf |website=developer.arm.com |access-date=5 July 2019 |pages=45–47 |language=en |archive-date=5 July 2019 |archive-url=https://web.archive.org/web/20190705083043/https://static.docs.arm.com/ihi0022/e/IHI0022E_amba_axi_and_ace_protocol_spec.pdf |url-status=dead }}</ref>

* FIXED
* INCR
* WRAP

In FIXED bursts, each beat within the transfer has the same address. This is useful for repeated access at the same memory location, such as when reading or writing a [[FIFO (computing and electronics)|FIFO]].

<math>\mathit{Address} = \mathit{StartAddress}</math>

In INCR bursts, on the other hand, each beat has an address equal to the previous one plus the transfer size. This burst type is commonly used to read or write sequential memory areas.

<math>\mathit{Address}_i = \mathit{StartAddress} + \mathit{i} \cdot \mathit{TransferSize}</math>

WRAP bursts are similar to the INCR ones, as each transfer has an address equal to the previous one plus the transfer size. However, with WRAP bursts, if the address of the current beat reaches the "Higher Address boundary", it is reset to the "Wrap boundary":

<math>\mathit{Address}_i = \mathit{WrapBoundary} + (\mathit{StartAddress} + \mathit{i} \cdot \mathit{TransferSize})\ \mathrm{mod}\ (\mathit{BurstLength} \cdot \mathit{TransferSize})</math>

with

<math>\mathit{WrapBoundary} = \left\lfloor \frac{\mathit{StartAddress}}{\mathit{NumberBytes} \cdot \mathit{BurstLength}} \right\rfloor \cdot (\mathit{NumberBytes} \cdot \mathit{BurstLength})</math>

=== Transactions ===

==== Reads ====
[[File:AXI read transaction.svg|thumb|upright=2.25|Example of an AXI read transaction. The initiator requests 4 beats (ARLEN + 1<ref name="axlen">{{cite web |author1=Arm Holdings |title=AMBA AXI and ACE Protocol Specification |url=https://static.docs.arm.com/ihi0022/e/IHI0022E_amba_axi_and_ace_protocol_spec.pdf |website=developer.arm.com |access-date=5 July 2019 |page=44 |language=en}}</ref>) of 4 Bytes each starting from address 0x0 with INCR type. The target returns 0x10 for address 0x0, 0x11 for address 0x4, 0x12 for address 0x8 and 0x13 for address 0xc, all with the OKAY status. Only the most relevant signals are shown here.]]

To start a read transaction, the initiator has to provide on the Read address channel:
* the start address on ARADDR
* the burst type, either FIXED, INCR or WRAP, on ARBURST (if present)
* the burst length on ARLEN (if present).
Additionally, the other auxiliary signals, if present, are used to define more specific transfers.

After the usual ARVALID/ARREADY handshake, the target has to provide on the Read data channel:
* the data corresponding to the specified address(es) on RDATA
* the status of each beat on RRESP
plus any other optional signals.
Each beat of the target's response is done with a RVALID/RREADY handshake and, on the last transfer, the target has to assert RLAST to inform that no more beats will follow without a new read request.

==== Writes ====
[[File:AXI write transaction.svg|thumb|upright=2.25|Example of an AXI write transaction. The initiator drives 4 beats (AWLEN + 1<ref name="axlen" />) of 4 Bytes each starting from address 0x0 with INCR type, writing 0x10 for address 0x0, 0x11 for address 0x4, 0x12 for address 0x8 and 0x13 for address 0xc. The target returns 'OKAY' as write response for the whole transaction. Only the most relevant signals are shown here.]]

To start a write operation, the initiator has to provide both the address information and the data information.

The address information is provided over the Write address channel, in a similar manner as a read operation:
* the start address has to be provided on AWADDR
* the burst type, either FIXED, INCR or WRAP, on AWBURST (if present)
* the burst length on AWLEN (if present)
and, if present, all the optional signals.

An initiator has also to provide the data related to the specified address(es) on the Write data channel:
* the data on WDATA
* the "strobe" bits on WSTRB (if present), which conditionally mark the individual WDATA bytes as "valid" or "invalid"

Like in the read path, on the last data word, WLAST has to be asserted by the initiator.

After the completion of both the transactions, the target has to send back to the initiator the status of the write over the Write response channel, by returning the result over the BRESP signal.