Editing Serial Peripheral Interface (section)

== Interoperability with other standards ==

=== Microwire ===
Microwire,<ref>[https://www.ti.com/lit/an/snoa743/snoa743.pdf MICROWIRE Serial Interface] National Semiconductor Application Note AN-452</ref> often spelled '''μWire''', is essentially a predecessor of SPI and a trademark of [[National Semiconductor]]. It's a strict subset of SPI: half-duplex, and using SPI mode 0. Microwire chips tend to need slower clock rates than newer SPI versions; perhaps 2&nbsp;MHz vs. 20&nbsp;MHz. Some Microwire chips also support a [[Serial Peripheral Interface#Three-wire|three-wire]] mode.

=== Microwire/Plus ===
Microwire/Plus<ref>[https://www.ti.com/lit/an/snoa093/snoa093.pdf MICROWIRE/PLUS Serial Interface for COP800 Family] National Semiconductor Application Note AN-579</ref> is an enhancement of Microwire and features full-duplex communication and support for SPI modes 0 and 1. There was no specified improvement in serial clock speed.

=== JTAG ===
{{Main articles|JTAG}}
Although there are some similarities between SPI and the [[JTAG]] (IEEE 1149.1-2013) protocol, they are not interchangeable. JTAG is specifically intended to provide reliable [[Boundary scan|test access to the I/O pins]] from an off-board controller with less precise signal delay and skew parameters, while SPI has many varied applications. While not strictly a level sensitive interface, the JTAG protocol supports the recovery of both setup and hold violations between JTAG devices by reducing the clock rate or changing the clock's duty cycles. Consequently, the JTAG interface is not intended to support extremely high data rates.<ref>IEEE 1149.1-2013</ref>