Editing Serial Peripheral Interface (section)

===Clock polarity and phase===
In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. Motorola<ref>[https://web.archive.org/web/20150413003534/http://www.ee.nmt.edu/~teare/ee308l/datasheets/S12SPIV3.pdf SPI Block Guide v3.06; Motorola/Freescale/NXP; 2003.]</ref><ref name=":4" /> named these two options as CPOL and CPHA (for '''c'''lock '''pol'''arity and '''c'''lock '''pha'''se) respectively, a convention most vendors have also adopted.

[[File:SPI timing diagram CS.svg|thumb|338x338px|SPI [[Digital timing diagram|timing diagram]] for both clock polarities and phases. Data bits output on blue lines if CPHA=0, or on red lines if CPHA=1, and sample on opposite-colored lines. Numbers identify data bits. Z indicates [[high impedance]].]]

The SPI [[digital timing diagram|timing diagram]] shown is further described below:
* CPOL represents the polarity of the clock. Polarities can be converted with a simple [[inverter (logic gate)|inverter]].
** SCLK{{Subscript|1=CPOL=0}} is a clock which idles at the [[logical low]] voltage.
** SCLK{{Subscript|1=CPOL=1}} is a clock which idles at the logical high voltage.
* CPHA represents the [[Phase (waves)|phase]] of each data bit's transmission cycle relative to SCLK.
** For CPHA=0:
*** The first data bit is output ''immediately'' when {{Overline|SS}} activates.
*** Subsequent bits are output when SCLK transitions ''to'' its idle voltage level.
*** Sampling occurs when SCLK transitions ''from'' its idle voltage level.
** For CPHA=1:
*** The first data bit is output on SCLK's first clock edge ''after'' {{Overline|SS}} activates.
*** Subsequent bits are output when SCLK transitions ''from'' its idle voltage level.
*** Sampling occurs when SCLK transitions ''to'' its idle voltage level.
** Conversion between these two phases is non-trivial.
** MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next bit's transmission cycle starts, so SPI master and slave devices may sample data at different points in that half cycle, for flexibility, despite the original specification.