Editing Bit manipulation instructions (section)

=== Power ISA ===
[[Power ISA]] has a large range of bit manipulation instructions,{{sfn|power3.1|loc=IBM Power ISA v3.1}} largely due to its history and relationship with IBM mainframes and the [[z/Architecture]]:
* [[Count leading zeros]] and trailing, and masked versions of the same.{{sfn|power3.1|loc=Power ISA Book I Chapter 3.3.13 Fixed-Point|p=104}} There is a mixture of [[popcount]]{{sfn|power3.1|loc=Power ISA Book I Chapter 3.3.13 Fixed-Point|p=104}} [[Parity bit|parity]]{{sfn|power3.1|loc=Power ISA Book I Chapter 3.3.13 Fixed-Point|p=103}} and [[SIMD within a register|SWAR]]-style instructions, but not a full set of each: {{code|popcntb}} is SWAR byte-level 8x8-bit but there is no 4x16-bit {{code|popcnth}} yet there is 2x32-bit {{code|popcntw}} and 64-bit scalar {{code|popcntd}}. Likewise, {{code|prtyw}} is SWAR half-word 4x16-bit but there is no {{code|prtyb}}
* masked bit-extract {{code|pextd}} and bit-deposit {{code|pdepd}} these drop and distribute bits in place according to a mask instead of the more usual technique of a offset and a length.;{{sfn|power3.1|loc=Power ISA Book I Chapter 3.3.13 Fixed-Point|p=106}} An unusual centrifuge instruction which moves masked-bits to the left and unmasked bits to the right, preserving their relative order in both instances. Most ISAs would have an operand expressing the number of sequential bits to extract, plus the length: {{code|cfuged}} combines these into one general-purpose bitmask.{{sfn|power3.1|loc=Power ISA Book I Chapter 3.3.13 Fixed-Point|p=106}} 
* 8x8-bit transpose {{code|vgbbd}}{{sfn|power3.1|loc=Power ISA Book I Chapter 6.12.1 Vector Facility|p=445}} which treats a 64-bit quantity as an 8x8 2D matrix, and performs a matrix transpose operation. Each bit 0 of each byte therefore becomes the first byte, each bit 1 of each byte becomes the second and so on.
* a strange but very useful indexing instruction, ({{code|bpermd}}){{sfn|power3.1|loc=Power ISA Book I Chapter 3.3.13 Fixed-Point|p=105}} which allows selection of up to eight individual bits from a 64-bit source, by treating each byte of a second 64-bit register as bit-indices into the first.
* Ternary 8-bit [[bitwise ternary logic instruction]] {{code|xxeval}}{{sfn|power3.1|loc=Power ISA Book I Chapter 7. Vector-Scalar Extension Facility|p=967}} similar to [[AVX-512]]
* strategic instructions for accelerating [[Binary-coded decimal#Packed BCD|packed BCD]]{{sfn|power3.1|loc=Power ISA Book I Chapter 3.3.15 Fixed-Point|p=117}} 
* Power v3.1 also introduced a number of additional bit manipulation instructions including swapping the order of bytes within half-words, words, and the whole 64-bit register.