Editing Serial Peripheral Interface (section)

=== Bit-width extensions ===

==== Dual SPI ====
For instances where the full-duplex nature of SPI is not used, an extension uses both data pins in a half-duplex configuration to send two bits per clock cycle. Typically a command byte is sent requesting a response in dual mode, after which the MOSI line becomes SIO0 (serial I/O 0) and carries even bits, while the MISO line becomes SIO1 and carries odd bits. Data is still transmitted most-significant bit first, but SIO1 carries bits 7, 5, 3 and 1 of each byte, while SIO0 carries bits 6, 4, 2 and 0.

This is particularly popular among SPI ROMs, which have to send a large amount of data, and comes in two variants:<ref name="W25Q16JV">{{cite web |title=W25Q16JV 3V 16M-bit serial flash memory with Dual/Quad SPI |date=12 August 2016 |version=Revision D |publisher=[[Winbond]] |type=data sheet |url=https://www.winbond.com/resource-files/w25q16jv%20spi%20revd%2008122016.pdf |access-date=2017-02-10}}</ref><ref name="D25LQ64">{{cite web |title=D25LQ64 1.8V Uniform Sector Dual and Quad SPI Flash |type=data sheet |date=11 February 2011 |version=version 0.1 |publisher=GigaDevice |url=https://www.sst-ic.com/File/DataSheet/KC909742-1112151725544ed0c4ce-8225-4c46-8d18-b81422086247.pdf |archive-url=https://web.archive.org/web/20170212090900/http://www.sst-ic.com/File/DataSheet/KC909742-1112151725544ed0c4ce-8225-4c46-8d18-b81422086247.pdf |url-status=dead |archive-date=12 February 2017 |access-date=2017-02-10}}</ref>

* Dual read sends the command and address from the master in single mode, and returns the data in dual mode.
* Dual I/O sends the command in single mode, then sends the address and return data in dual mode.

==== Quad SPI ====
'''Quad SPI''' ('''QSPI'''; different to but has same abbreviation as ''Queued-SPI'' described in {{Slink|2=Intelligent SPI controllers|nopage=y}}) goes beyond dual SPI, adding two more I/O lines (SIO2 and SIO3) and sends 4 data bits per clock cycle. Again, it is requested by special commands, which enable quad mode after the command itself is sent in single mode.{{r|W25Q16JV|D25LQ64}}

; SQI Type 1: Commands sent on single line but addresses and data sent on four lines
; SQI Type 2: Commands and addresses sent on a single line but data sent/received on four lines

==== QPI/SQI ====
Further extending quad SPI, some devices support a "quad everything" mode where ''all'' communication takes place over 4 data lines, including commands.<ref>{{cite web |url=https://community.nxp.com/thread/336422 |title=QuadSPI flash: Quad SPI mode vs. QPI mode |date=December 2014 |website=NXP community forums |access-date=2016-02-10}}</ref>   This is variously called "QPI"{{r|D25LQ64}} (not to be confused with [[Intel QuickPath Interconnect]]) or "serial quad I/O" (SQI)<ref name="SST26VF032B">{{cite web |title=SST26VF032B / SST26VF032BA 2.5V/3.0V 32 Mbit Serial Quad I/O (SQI) Flash Memory |type=Data sheet |publisher=[[Microchip, Inc.]] |date=2017 |version=version E |url=http://ww1.microchip.com/downloads/en/DeviceDoc/20005218E.pdf |access-date=2017-02-10}}</ref>

This requires programming a configuration bit in the device and requires care after reset to establish communication.