Editing Intel QuickPath Interconnect (section)

==Implementation==
[[File:Intel Nehalem arch.svg|thumb|right|upright=2.2|QPI is an [[uncore]] component in Intel's [[Nehalem (microarchitecture)|Nehalem]] microarchitecture.]]

The QPI is an element of a system architecture that Intel calls the ''QuickPath architecture'' that implements what Intel calls ''QuickPath technology''.<ref>{{cite web |title=Intel Demonstrates Industry's First 32nm Chip and Next-Generation Nehalem Microprocessor Architecture |url= http://www.intel.com/pressroom/archive/releases/20070918corp_a.htm?iid=tech_arch_32nm+body_pressrelease |access-date=2007-12-31 |archive-url=https://web.archive.org/web/20080102101316/http://www.intel.com/pressroom/archive/releases/20070918corp_a.htm?iid=tech_arch_32nm+body_pressrelease |archive-date=2008-01-02}}</ref> In its simplest form on a single-processor motherboard, a single QPI is used to connect the processor to the IO Hub (e.g., to connect an [[Intel Core i7]] to an [[Intel X58|X58]]). In more complex instances of the architecture, separate QPI link pairs connect one or more processors and one or more IO hubs or routing hubs in a network on the motherboard, allowing all of the components to access other components via the network. As with HyperTransport, the QuickPath Architecture assumes that the processors will have integrated [[memory controller]]s, and enables a [[non-uniform memory access]] (NUMA) architecture.

Each QPI comprises two 20-lane point-to-point data links, one in each direction ([[full duplex]]), with a separate clock pair in each direction, for a total of 42 signals. Each signal is a [[differential signaling|differential pair]], so the total number of pins is 84. The 20 data lanes are divided onto four "quadrants" of 5 lanes each. The basic unit of transfer is the 80-bit [[flit (computer networking)|flit]], which has 8 bits for error detection, 8 bits for "link-layer header", and 64 bits for data. One 80-bit flit is transferred in two clock cycles (four 20-bit transfers, two per clock tick.) QPI bandwidths are advertised by computing the transfer of 64 bits (8 bytes) of data every two clock cycles in each direction.<ref name="realworld">{{cite web |title= The Common System Interface: Intel's Future Interconnect |work= Real World Tech |author= David Kanter |date= August 28, 2007 |url= http://www.realworldtech.com/common-system-interface/ |access-date= August 14, 2014 }}</ref>

Although the initial implementations use single four-quadrant links, the QPI specification permits other implementations. Each quadrant can be used independently. On high-reliability servers, a QPI link can operate in a degraded mode. If one or more of the 20+1 signals fails, the interface will operate using 10+1 or even 5+1 remaining signals, even reassigning the clock to a data signal if the clock fails.<ref name="realworld"/>  The initial Nehalem implementation used a full four-quadrant interface<!-- what is that? --> to achieve 25.6&nbsp;GB/s (6.4GT/s × 1 byte × 4), which provides exactly double the theoretical bandwidth of Intel's 1600&nbsp;MHz FSB used in the X48 chipset.

Although some high-end Core i7 processors expose QPI, other "mainstream" Nehalem desktop and mobile processors intended for single-socket boards (e.g. [[LGA 1156]] Core i3, Core i5, and other Core i7 processors from the [[Lynnfield (microprocessor)|Lynnfield]]/[[Clarksfield (microprocessor)|Clarksfield]] and successor families) do not expose QPI externally, because these processors are not intended to participate in multi-socket systems.

However, QPI is used internally on these chips to communicate with the "[[uncore]]", which is part of the chip containing memory controllers, CPU-side [[PCI Express]] and GPU, if present; the uncore may or may not be on the same die as the CPU core, for instance it is on a separate die in the [[Westmere (microarchitecture)|Westmere]]-based [[Clarkdale (microprocessor)|Clarkdale]]/[[Arrandale]].<ref>{{cite web|author=Chris Angelini |url=http://www.tomshardware.com/reviews/intel-core-i5,2410-3.html |title=QPI, Integrated Memory, PCI Express, And LGA 1156 - Intel Core i5 And Core i7: Intel's Mainstream Magnum Opus |publisher=Tomshardware.com |date=2009-09-07 |access-date=2014-01-21}}</ref><ref>{{cite web|author=Published on 25th January 2010 by Richard Swinburne |url=http://www.bit-tech.net/hardware/graphics/2010/01/25/intel-gma-hd-graphics-performance/1 |title=Feature - Intel GMA HD Graphics Performance |publisher=bit-tech.net |date=2010-01-25 |access-date=2014-01-21}}</ref><ref>{{cite web|url=http://hexus.net/tech/features/cpu/20419-intel-clarkdale-32nm-cpu-and-gpu-chip-benchmarked-again/ |title=Intel Clarkdale 32nm CPU-and-GPU chip benchmarked (again) - CPU - Feature |publisher=HEXUS.net |date=2009-09-25 |access-date=2014-01-21}}</ref><ref name="hotchips-2nd-gen">{{cite web
 | url = http://www.hotchips.org/wp-content/uploads/hc_archives/hc23/HC23.19.9-Desktop-CPUs/HC23.19.911-Sandy-Bridge-Lempel-Intel-Rev%207.pdf
 | title = 2nd Generation Intel Core Processor Family: Intel Core i7, i5 and i3
 | date = 2013-07-28
 | access-date = 2014-01-21
 | author = Oded Lempel
 | website = hotchips.org
 | archive-date = 2020-07-29
 | archive-url = https://web.archive.org/web/20200729000210/http://www.hotchips.org/wp-content/uploads/hc_archives/hc23/HC23.19.9-Desktop-CPUs/HC23.19.911-Sandy-Bridge-Lempel-Intel-Rev%207.pdf
 | url-status = dead
 }}</ref>{{rp|3}}

In post-2009 single-socket chips starting with Lynnfield, Clarksfield, Clarkdale and Arrandale, the traditional [[Northbridge (computing)|northbridge]] functions are integrated into these processors, which therefore communicate externally via the slower [[Direct Media Interface|DMI]] and PCI Express interfaces.

Thus, there is no need to incur the expense of exposing the (former) front-side bus interface via the processor socket.<ref>Lily Looi, Stephan Jourdan, [http://www.hotchips.org/wp-content/uploads/hc_archives/hc21/2_mon/HC21.24.400.ClientProcessors-Epub/HC21.24.442.Looi-Intel_NhmClient_Hotchips2009b.pdf Transitioning the Intel® Next Generation Microarchitectures (Nehalem and Westmere) into the Mainstream] {{Webarchive|url=https://web.archive.org/web/20200802042642/http://www.hotchips.org/wp-content/uploads/hc_archives/hc21/2_mon/HC21.24.400.ClientProcessors-Epub/HC21.24.442.Looi-Intel_NhmClient_Hotchips2009b.pdf |date=2020-08-02 }}, Hot Chips 21, August 24, 2009</ref>

Although the core–uncore QPI link is not present in desktop and mobile [[Sandy Bridge]] processors (as it was on Clarkdale, for example), the internal ring interconnect between on-die cores is also based on the principles behind QPI, at least as far as [[cache coherency]] is concerned.<ref name="hotchips-2nd-gen" />{{rp|10}}