Editing Bit manipulation instructions (section)

=== Intel and AMD (x86) ===
* The x86 instruction core set contains:
** {{code|BSR}} Bit Scan Reverse - Returns bit index of highest set bit in input, effectively backwards count leading zeros, not defined for 0.
** {{code|BSF}} Bit Scan Forward - Returns bit index of lowest set bit in input, effectively count trailing zeros, but not defined for 0.
* [[SSE4]] and the [[X86 Bit manipulation instruction set|BMI]] instruction set extensions contains instructions for:
** Count leading zeros - {{code|lzcnt}}
** Count trailing zeros - {{code|tzcnt}}
** Population count - {{code|popcnt}}
** Bit extract/bit deposit - {{code|pext}}/{{code|pdep}}
** Bit test - {{code|ptest}} and {{code|vptest}}, given two inputs, do both an {{code|AND}} operation and an {{code|ANDN}} operation between them, and set the ZF and CF EFLAGS bits on whether the results of the AND and ANDN, respectively, are 0. This can be used to test if all masked bits are zero, all masked bits are set, or a mix.
* The [[AVX-512#Bitwise ternary logic|AVX-512 ternary]] extension includes a [[bitwise ternary logic instruction]], {{code|vpternlog}}. Also noteworthy is a conflict detection instruction, [[AVX-512#Conflict detection|<code>VPCONFLICTD</code>]]
* Also present in the AVX/[[AVX-512]] [[GFNI instruction set|GFNI subset]] is bit-matrix affine transformation and its inverse: {{code|GF2P8AFFINEQB}} is effectively an 8x8 bit-matrix multiply in the [[Galois field]] GF(2^8).<ref>{{cite web | title=GF2P8AFFINEQB — Galois Field Affine Transformation | url=https://www.felixcloutier.com/x86/gf2p8affineqb }}</ref>
* AVX-512 BITALG besides AVX-512 version of existing bit manipulation instruction, also added {{code|VPSHUFBITQMB}} which is a bit-level shuffle instruction, that picks bits from one source using indexes in the second source.
* An Intel GNFI technology guide on that AVX/AVX512 GNFI Extension also lists numerous uses including parallel byte-wise set/clear/invert bitmanipulation, 5-bit sign-extension and points out the potential is much greater.<ref name=gfni>{{cite web |title=Galois Field New Instructions (GFNI) Technology Guide |url=https://networkbuilders.intel.com/solutionslibrary/galois-field-new-instructions-gfni-technology-guide |website=networkbuilders.intel.com |language=en}}</ref>
* [[Intel BCD opcodes]]