Editing Advanced eXtensible Interface (section)

== Handshake ==
[[File:AMBA_AXI_Handshake.svg|thumb|Basic [[Handshake (computing)|handshake mechanism]] of the AMBA AXI [[Communication protocol|protocol]]. In this example, the destination entity waits for a high VALID to assert its own READY.]]

AXI defines a basic [[Handshake (computing)|handshake mechanism]], composed by an <code>xVALID</code> and <code>xREADY</code> signal.<ref>{{cite web |author1=Arm Holdings |title=AMBA AXI and ACE Protocol Specification |url=https://static.docs.arm.com/ihi0022/e/IHI0022E_amba_axi_and_ace_protocol_spec.pdf |website=developer.arm.com |access-date=5 July 2019 |pages=37–38 |language=en |archive-date=5 July 2019 |archive-url=https://web.archive.org/web/20190705083043/https://static.docs.arm.com/ihi0022/e/IHI0022E_amba_axi_and_ace_protocol_spec.pdf |url-status=dead }}</ref> The <code>xVALID</code> signal is driven by the source to inform the destination entity that the payload on the channel is valid and can be read from that [[clock cycle]] onwards. Similarly, the <code>xREADY</code> signal is driven by the receiving entity to notify that it is prepared to receive data.

When both the <code>xVALID</code> and <code>xREADY</code> signals are high in the same [[clock cycle]], the data payload is considered transferred and the source can either provide a new data payload, by keeping high <code>xVALID</code>, or terminate the transmission, by de-asserting <code>xVALID</code>. An individual data transfer, so a clock cycle when both <code>xVALID</code> and <code>xREADY</code> are high, is called a "beat".

Two main rules are defined for the control of these signals:

* A source must not wait for a high <code>xREADY</code> to assert <code>xVALID</code>.
* Once <code>xVALID</code> is asserted, a source must maintain the assertion until a handshake occurs.

Thanks to this [[Handshake (computing)|handshake]] mechanism, both the source and the destination can control the flow of data, throttling the speed if needed.