Editing Serial Peripheral Interface (section)

===Multidrop configuration===
[[File:SPI_three_slaves.svg|thumb|216x216px|Multidrop SPI bus]]
In the [[multidrop bus]] configuration, each slave has its own {{Overline|SS}}, and the master selects only one at a time. MISO, SCLK, and MOSI are each shared by all devices. This is the way SPI is normally used.

Since the MISO pins of the slaves are connected together, they are required to be tri-state pins (high, low or high-impedance), where the high-impedance output must be applied when the slave is not selected. Slave devices not supporting tri-state may be used in multidrop configuration by adding a tri-state buffer chip controlled by its {{Overline|SS}} signal.<ref name="Better SPI Bus Design in 3 Steps">[https://www.pjrc.com/better-spi-bus-design-in-3-steps/ Better SPI Bus Design in 3 Steps]</ref> (Since only a single signal line needs to be tristated per slave, one typical standard logic chip that contains four tristate buffers with independent gate inputs can be used to interface up to four slave devices to an SPI bus)<blockquote>Caveat: All {{Overline|SS}} signals should start high (to indicate no slaves are selected) before sending initialization messages to any slave, so other uninitialized slaves ignore messages not addressed to them. This is a concern if the master uses [[General-purpose input/output|general-purpose input/output (GPIO) pins]] (which may default to an undefined state) for {{Overline|SS}} and if the master uses separate software libraries to initialize each device. One solution is to configure all GPIOs used for {{Overline|SS}} to output a high voltage for ''all'' slaves ''before'' running initialization code from any of those software libraries. Another solution is to add a [[pull-up resistor]] on each {{Overline|SS}}, to ensure that all {{Overline|SS}} signals are initially high.<ref name="Better SPI Bus Design in 3 Steps" /></blockquote>