Editing Advanced eXtensible Interface (section)

== Subsets ==

=== AXI-Lite ===
AXI4-Lite is a [[subset]] of the AXI4 protocol, providing a [[Processor register|register-like]] structure with reduced features and complexity.<ref>{{cite web |author1=Arm Holdings |title=AMBA AXI and ACE Protocol Specification |url=https://static.docs.arm.com/ihi0022/e/IHI0022E_amba_axi_and_ace_protocol_spec.pdf |website=developer.arm.com |access-date=5 July 2019 |pages=121–128 |language=en |archive-date=5 July 2019 |archive-url=https://web.archive.org/web/20190705083043/https://static.docs.arm.com/ihi0022/e/IHI0022E_amba_axi_and_ace_protocol_spec.pdf |url-status=dead }}</ref> Notable differences are:
* all bursts are composed by 1 beat only
* all data accesses use the full data bus width, which can be either 32 or 64 bits

AXI4-Lite removes part of the AXI4 signals but follows the AXI4 specification for the remaining ones. Being a [[subset]] of AXI4, AXI4-Lite transactions are fully compatible with AXI4 devices, permitting the [[interoperability]] between AXI4-Lite initiators and AXI4 targets without additional conversion logic.<ref>{{cite web |author1=Arm Holdings |title=AMBA AXI and ACE Protocol Specification |url=https://static.docs.arm.com/ihi0022/e/IHI0022E_amba_axi_and_ace_protocol_spec.pdf |website=developer.arm.com |access-date=5 July 2019 |page=124 |language=en |archive-date=5 July 2019 |archive-url=https://web.archive.org/web/20190705083043/https://static.docs.arm.com/ihi0022/e/IHI0022E_amba_axi_and_ace_protocol_spec.pdf |url-status=dead }}</ref>

==== Signals ====

{| class="wikitable"
|-
! Write address channel !! Write data channel !! Write response channel !! Read address channel !! Read data channel
|-
| AWVALID || WVALID || BVALID || ARVALID || RVALID
|-
| AWREADY || WREADY || BREADY || ARREADY || RREADY
|-
| AWADDR || WDATA || BRESP || ARADDR || RDATA
|-
| AWPROT || WSTRB || || ARPROT || RRESP
|}
<ref>{{cite web |author1=Arm Holdings |title=AMBA AXI and ACE Protocol Specification |url=https://static.docs.arm.com/ihi0022/e/IHI0022E_amba_axi_and_ace_protocol_spec.pdf |website=developer.arm.com |access-date=5 July 2019 |page=122 |language=en |archive-date=5 July 2019 |archive-url=https://web.archive.org/web/20190705083043/https://static.docs.arm.com/ihi0022/e/IHI0022E_amba_axi_and_ace_protocol_spec.pdf |url-status=dead }}</ref>

=== AXI-Stream ===
AXI4-Stream is a simplified, lightweight bus protocol designed specifically for high-speed streaming data applications. It supports only unidirectional data flow, without the need for addressing or complex handshaking. An AXI Stream is similar to an AXI write data channel, with some important differences on how the data is arranged:
* no bursts, instead data is packed into packets, frames and data streams
* no limit on the data length which may be continuous
* data width can be any integer number of bytes

AXI5 Stream protocol introduces wake-up signaling and signal protection using parity.

A single AXI Stream transmitter can drive multiple streams which may be interleaved but reordering is not permitted.

{| class="wikitable"
|-
! Signal !! Source !! Width !! Description
|-
| ACLK || Clock || 1 || ACLK is a global clock signal. All signals are sampled on the rising edge of ACLK.
|-
| ARESETn || Reset || 1 || ARESETn is a global reset signal.
|-
| TVALID || Transmitter || 1 || TVALID indicates the Transmitter is driving a valid transfer. A transfer takes place when both TVALID and TREADY are asserted.
|-
| TREADY || Receiver || 1 || TREADY indicates that a Receiver can accept a transfer.
|-
| TDATA || Transmitter || TDATA_WIDTH || TDATA is the primary payload used to provide the data that is passing across the interface. TDATA_WIDTH must be an integer number of bytes and is recommended to be 8, 16, 32, 64, 128, 256, 512 or 1024-bits.
|-
| TSTRB || Transmitter || TDATA_WIDTH/8 || TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
|-
| TKEEP || Transmitter || TDATA_WIDTH/8 || TKEEP is the byte qualifier that indicates whether content of the associated byte of TDATA is processed as part of the data stream.
|-
| TLAST || Transmitter || 1 || TLAST indicates the boundary of a packet.
|-
| TID || Transmitter || TID_WIDTH || TID is a data stream identifier. TID_WIDTH is recommended to be no more than 8.
|-
| TDEST || Transmitter || TDEST_WIDTH || TDEST provides routing information for the data stream. TDEST_WIDTH is recommended to be no more than 8.
|-
| TUSER || Transmitter || TUSER_WIDTH || TUSER is a user-defined sideband information that can be transmitted along the data stream. TUSER_WIDTH is recommended to be an integer multiple of TDATA_WIDTH/8.
|-
| TWAKEUP || Transmitter || 1 || TWAKEUP identifies any activity associated with AXI-Stream interface.
|}