Editing Serial Peripheral Interface (section)

==Operation==
[[File:SPI_single_slave.svg|thumb|368x368px|Single master to single slave: basic SPI wiring]]

Commonly, SPI has four logic signals. [[#Variations|Variations]] may use different [[#Alternative terminology|names]] or have different signals.

:{| class="wikitable"
! Abbr.!! Name !! Description
|-
| {{center|{{Overline|SS}}}} || {{center|Slave Select}} || [[Logic level#Active state|Active-low]] [[chip select]] signal from master to<br />enable communication with a specific slave device
|-
| {{center|SCLK}} || {{center|Serial Clock}} || [[Clock signal]] from master
|-
| {{center|MOSI}} || {{center|Master Out Slave In}} || [[Serial communication|Serial data]] output from master
|-
| {{center|MISO}} || {{center|Master In Slave Out}}  || [[Serial communication|Serial data]] output from slave
|}

MOSI on a master outputs to MOSI on a slave. MISO on a slave outputs to MISO on a master.

Each device internally uses a [[shift register]] for serial communication, which together forms an inter-chip [[circular buffer]].

To support multidrop bus, slave devices should use [[tri-state output]]s so their MISO signal becomes [[high impedance]] (electrically disconnected) when the device is not selected. Slaves without tri-state outputs cannot share a MISO line with other slaves without using an external tri-state buffer.

===Data transmission===
[[File:SPI 8-bit circular transfer.svg|upright=1.8|thumb|A typical hardware setup using two [[shift register]]s to form an inter-chip [[circular buffer]] ]]
[[File:Serial_Peripheral_Interface_Animation.gif|thumb|Serial Peripheral Interface animation. This animation shows a scenario where the master sends 8-bit data and simultaneously reads 16-bit data from the slave. The lower boxes represent the device's memories.]]

To begin communication, the SPI master first selects the device it wants to communicate with by pulling its {{Overline|SS}} low. (The bar above {{Overline|SS}} indicates it is an [[active low]] signal, so a low voltage means "selected", while a high voltage means "not selected")

If a waiting period is required, such as for an analog-to-digital conversion, the master must wait for at least that period of time before issuing clock cycles.{{NoteTag|Some slaves require a falling edge of the {{Overline|Slave Select}} signal to initiate an action. An example is the Maxim MAX1242 ADC, which starts conversion on a high→low transition.}}

During each SPI clock cycle, full-duplex transmission of a single bit occurs. The master sends a bit on the MOSI line while the slave sends a bit on the MISO line, and then each reads their corresponding incoming bit. This sequence is maintained even when only one-directional data transfer is intended.

Transmission using a single slave involves one shift register in the master and one shift register in the slave, both of some given word size (e.g. 8 bits). The transmissions often consist of eight-bit words, but other word-sizes are also common, for example, sixteen-bit words for touch-screen controllers or audio codecs, such as the TSC2101 by Texas Instruments, or twelve-bit words for many digital-to-analog or analog-to-digital converters. 

Data is usually shifted out with the [[most-significant bit]] (MSB) first but the original specification has a LSBFE ("LSB-First Enable") to control whether data is transferred least (LSB) or most significant bit (MSB) first. On the clock edge, both master and slave shift out a bit to its counterpart. On the next clock edge, each receiver samples the transmitted bit and stores it in the shift register as the new least-significant bit. After all bits have been shifted out and in, the master and slave have exchanged register values. If more data needs to be exchanged, the shift registers are reloaded and the process repeats. Transmission may continue for any number of clock cycles. When complete, the master stops toggling the clock signal, and typically deselects the slave.

If a single slave device is used, its {{Overline|SS}} pin ''may'' be fixed to [[logic level|logic low]] if the slave permits it. With multiple slave devices, a [[#Multidrop configuration|multidrop configuration]] requires an independent {{Overline|SS}} signal from the master for each slave device, while a [[#Daisy chain configuration|daisy-chain configuration]] only requires one {{Overline|SS}} signal.

Every slave on the bus that has not been selected should disregard the input clock and MOSI signals. And to prevent [[Bus contention|contention]] on MISO, non-selected slaves must use [[Three-state logic|tristate]] output. Slaves that are not already tristate will need external tristate buffers to ensure this.<ref name="Better SPI Bus Design in 3 Steps" />

{{clear}}

===Clock polarity and phase===
In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. Motorola<ref>[https://web.archive.org/web/20150413003534/http://www.ee.nmt.edu/~teare/ee308l/datasheets/S12SPIV3.pdf SPI Block Guide v3.06; Motorola/Freescale/NXP; 2003.]</ref><ref name=":4" /> named these two options as CPOL and CPHA (for '''c'''lock '''pol'''arity and '''c'''lock '''pha'''se) respectively, a convention most vendors have also adopted.

[[File:SPI timing diagram CS.svg|thumb|338x338px|SPI [[Digital timing diagram|timing diagram]] for both clock polarities and phases. Data bits output on blue lines if CPHA=0, or on red lines if CPHA=1, and sample on opposite-colored lines. Numbers identify data bits. Z indicates [[high impedance]].]]

The SPI [[digital timing diagram|timing diagram]] shown is further described below:
* CPOL represents the polarity of the clock. Polarities can be converted with a simple [[inverter (logic gate)|inverter]].
** SCLK{{Subscript|1=CPOL=0}} is a clock which idles at the [[logical low]] voltage.
** SCLK{{Subscript|1=CPOL=1}} is a clock which idles at the logical high voltage.
* CPHA represents the [[Phase (waves)|phase]] of each data bit's transmission cycle relative to SCLK.
** For CPHA=0:
*** The first data bit is output ''immediately'' when {{Overline|SS}} activates.
*** Subsequent bits are output when SCLK transitions ''to'' its idle voltage level.
*** Sampling occurs when SCLK transitions ''from'' its idle voltage level.
** For CPHA=1:
*** The first data bit is output on SCLK's first clock edge ''after'' {{Overline|SS}} activates.
*** Subsequent bits are output when SCLK transitions ''from'' its idle voltage level.
*** Sampling occurs when SCLK transitions ''to'' its idle voltage level.
** Conversion between these two phases is non-trivial.
** MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next bit's transmission cycle starts, so SPI master and slave devices may sample data at different points in that half cycle, for flexibility, despite the original specification.

===Mode numbers ===
The combinations of polarity and phases are referred to by these "SPI mode" numbers with CPOL as the high order bit and CPHA as the low order bit:
{| class="wikitable"
|-
! SPI mode
! Clock polarity<br />(CPOL)
! Clock phase<br />(CPHA)
!Data is shifted out on
! Data is sampled on
|-
| 0 || 0 || 0 
|falling SCLK, and when {{Overline|SS}} activates || rising SCLK
|-
| 1 || 0 || 1 
| rising SCLK || falling SCLK
|-
| 2 || 1 || 0 
| rising SCLK, and when {{Overline|SS}} activates || falling SCLK
|-
| 3 || 1 || 1 
|falling SCLK|| rising SCLK
|}

Notes:

* Another commonly used notation represents the mode as a (CPOL, CPHA) tuple; e.g., the value '(0, 1)' would indicate CPOL=0 and CPHA=1.
* In Full Duplex operation, the master device could transmit and receive with different modes. For instance, it could transmit in Mode 0 and be receiving in Mode 1 at the same time.
* Different vendors may use different naming schemes, like CKE for clock edge or NCPHA for the inversion of CPHA.

=== Valid communications ===
Some slave devices are designed to ignore any SPI communications in which the number of clock pulses is greater than specified. Others do not care, ignoring extra inputs and continuing to shift the same output bit. It is common for different devices to use SPI communications with different lengths, as, for example, when SPI is used to access an IC's [[scan chain]] by issuing a command word of one size (perhaps 32 bits) and then getting a response of a different size (perhaps 153 bits, one for each pin in that scan chain).

===Interrupts===
Interrupts are outside the scope of SPI; their usage is neither forbidden nor specified, and so may be implemented optionally.

==== From master to slave ====
Microcontrollers configured as slave devices may have hardware support for generating interrupt signals to themselves when data words are received or overflow occurs in a receive [[FIFO (electronic)|FIFO]] buffer,<ref>{{Cite web |date=2002 |title=TMS320x281x Serial Peripheral Interface Reference Guide |url=https://www.ti.com/lit/pdf/spru059 |website=[[Texas Instruments]] |pages=16–17}}</ref> and may also set up an interrupt routine when their slave select input line is pulled low or high.

==== From slave to master ====
SPI slaves sometimes use an [[out-of-band signal]] (another wire) to send an interrupt signal to a master. Examples include pen-down interrupts from [[touchscreen]] sensors, thermal limit alerts from [[List of temperature sensors|temperature sensors]], alarms issued by [[real-time clock]] chips, [[Secure Digital#SDIO|SDIO]]{{NoteTag|Not to be confused with the SDIO (Serial Data I/O) line of the half-duplex implementation of SPI sometimes also called "3-wire" SPI. Here e.g. MOSI (via a resistor) and MISO (no resistor) of a master is connected to the SDIO line of a slave.|name=3wireSDI}} and [[audio jack]] insertions for an [[audio codec]]. Interrupts to master may also be faked by using [[Polling (computer science)|polling]] (similarly to [[USB 1.1]] and [[USB 2.0|2.0]]).