Editing Coherent Accelerator Processor Interface (section)

== History ==
The performance scaling traditionally associated with [[Moore's Law]]—dating back to 1965—began to taper off around 2004, as both Intel's [[Pentium 4#Prescott|Prescott]] architecture and IBM's [[Cell (microprocessor)|Cell processor]] pushed toward a 4&nbsp;GHz operating frequency.  Here both projects ran into a thermal scaling wall, whereby heat extraction problems associated with further increases in operating frequency largely outweighed gains from shorter cycle times.

Over the decade that followed, few commercial CPU products exceeded 4&nbsp;GHz, with the majority of performance improvements now coming from incrementally improved microarchitectures, better systems integration, and higher compute density—this largely in the form of packing a larger numbers of independent cores onto the same die, often at the ''expense'' of peak operating frequency (Intel's 24-core Xeon E7-8890 from June 2016 has a base operating frequency of just 2.2&nbsp;GHz, so as to operate within the constraints of a single-socket 165 W power consumption and cooling budget).

Where large performance gains have been realized, it was often associated with increasingly specialized compute units, such as GPU units added to the processor die, or external GPU- or FPGA-based accelerators. In many applications, accelerators struggle with limitations of the interconnect's performance (bandwidth and latency) or with limitations due to the interconnect's architecture (such as lacking memory coherence). Especially in the datacenter, improving the interconnect became paramount in moving toward a heterogeneous architecture in which hardware becomes increasingly tailored to specific compute workloads.

CAPI was developed to enable computers to more easily and efficiently attach specialized accelerators. Memory intensive and computation intensive works like [[matrix multiplication]]s for deep [[neural network]]s can be offloaded into CAPI-supported platforms.<ref>{{cite book | chapter = Accelerating HotSpots in Deep Neural Networks on a CAPI-Based FPGA | publisher = IEEE | author = Md Syadus Sefat, Semih Aslan, Jeffrey W Kellington, Apan Qasem | title = 2019 IEEE 21st International Conference on High Performance Computing and Communications; IEEE 17th International Conference on Smart City; IEEE 5th International Conference on Data Science and Systems (HPCC/Smart ''City''/DSS) | date=2019-10-03 | pages = 248–256 | doi = 10.1109/HPCC/SmartCity/DSS.2019.00048 | isbn = 978-1-7281-2058-4 | s2cid = 203656070 }}</ref> It was designed by IBM for use in its [[POWER8]] based systems which came to market in 2014. At the same time, IBM and several other companies founded the [[OpenPOWER Foundation]] to build an ecosystem around [[IBM Power microprocessors|Power]] based technologies, including CAPI. In October 2016 several OpenPOWER partners formed the ''OpenCAPI Consortium'' together with GPU and CPU designer [[AMD]] and systems designers [[Dell EMC]] and [[Hewlett Packard Enterprise]] to spread the technology beyond the scope of OpenPOWER and IBM.<ref>[https://web.archive.org/web/20161014220034/http://www.anandtech.com/show/10759/opencapi-unveiled-amd-ibm-google-more OpenCAPI Unveiled: AMD, IBM, Google, Xilinx, Micron and Mellanox Join Forces in the Heterogenous Computing Era]</ref>

On August 1, 2022, OpenCAPI specifications and assets were transferred to the [[Compute Express Link]] (CXL) Consortium.<ref>[https://web.archive.org/web/20220802125039/https://www.computeexpresslink.org/_files/ugd/0c1418_d3474155dc6e4929aa2a5658a894d1a6.pdf CXL Consortium and OpenCAPI Consortium Sign Letter of Intent to Transfer OpenCAPI Specifications to CXL]</ref>