Editing Advanced eXtensible Interface (section)

== Thread IDs==
{{Unreferenced section|date=May 2020}}

Thread IDs allow a single initiator port to support multiple threads, where each thread has in-order access to the AXI address space, however each thread ID initiated from a single initiator port may complete out of order with respect to each other.  For instance in the case where one thread ID is blocked by a slow peripheral, another thread ID may continue independently of the order of the first thread ID.  Another example, one thread on a [[CPU]] may be assigned a thread ID for a particular initiator port memory access such as read addr1, write addr1, read addr1, and this sequence will complete in order because each transaction has the same initiator port thread ID. Another thread running on the CPU may have another initiator port thread ID assigned to it, and its memory access will be in order as well but may be intermixed with the first thread IDs transactions.<ref>{{cite pdf |title=AMBA AXI and ACE Protocol Specification|url=https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/IHI0022H_amba_axi_protocol_spec.pdf|publisher=Arm Ltd.|date=22 February 2013|access-date=28 November 2025}}</ref>

Thread IDs on an initiator port are not globally defined, thus an AXI switch with multiple initiator ports will internally prefix the initiator port index to the thread ID, and provide this concatenated thread ID to the target device, then on return of the transaction to its initiator port of origin, this thread ID prefix will be used to locate the initiator port and the prefix will be truncated.  This is why the target port thread ID is wider in bits than the initiator port thread ID.<ref>{{cite pdf |title=AXI Interconnect v2.1 LogiCORE IP Product Guide|url=https://www.xilinx.com/support/documents/ip_documentation/axi_interconnect/v2_1/pg059-axi-interconnect.pdf|publisher=Xilinx|date=17 May 2022|access-date=28 November 2025}}</ref>

AXI-Lite bus is an AXI bus that only supports a single ID thread per initiator.  This bus is typically used for an end point that only needs to communicate with a single initiator device at a time, for example, a simple peripheral such as a [[UART]].  In contrast, a CPU is capable of initiating transactions to multiple peripherals and address spaces at a time, and will support more than one thread ID on its AXI initiator ports and AXI target ports.  This is why a CPU will typically support a full spec AXI bus.  A typical example of a front side AXI switch would include a full specification AXI initiator connected to a CPU initiator, and several AXI-Lite targets connected to the AXI switch from different peripheral devices.<ref>{{cite pdf |title=AXI Thread IDs (TIDs) – SoC Basics|url=https://www.isec.tugraz.at/wp-content/uploads/2021/08/p2.pdf|publisher=Institute for Embedded Systems, TU Graz|date=2021|access-date=28 November 2025}}</ref>

(Additionally, the AXI-Lite bus is restricted to only support transaction lengths of a single data word per transaction.)